Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Removed IOBUF's from sdc_controller.

Browse Source
This commit is contained in:
Jacob Pease 2023-01-27 14:35:34 -06:00
parent 67f0fee3b0
commit eb3c6754f8
3 changed files with 259 additions and 115 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

216
fpga/src/fpgaTop.v
View File

@ -267,39 +267,60 @@ module fpgaTop
wire s01_axi_rready;
// Output Interface
wire [31:0]axi4in_axi_awaddr;
wire [7:0]axi4in_axi_awlen;
wire [2:0]axi4in_axi_awsize;
wire [1:0]axi4in_axi_awburst;
wire [0:0]axi4in_axi_awlock;
wire [3:0]axi4in_axi_awcache;
wire [2:0]axi4in_axi_awprot;
wire [3:0]axi4in_axi_awregion;
wire [3:0]axi4in_axi_awqos;
wire axi4in_axi_awvalid;
wire axi4in_axi_awready;
wire [31:0]axi4in_axi_wdata;
wire [3:0]axi4in_axi_wstrb;
wire axi4in_axi_wlast;
wire axi4in_axi_wvalid;
wire axi4in_axi_wready;
wire [1:0]axi4in_axi_bresp;
wire axi4in_axi_bvalid;
wire axi4in_axi_bready;
wire [31:0]axi4in_axi_araddr;
wire [7:0]axi4in_axi_arlen;
wire [2:0]axi4in_axi_arsize;
wire [1:0]axi4in_axi_arburst;
wire [0:0]axi4in_axi_arlock;
wire [3:0]axi4in_axi_arcache;
wire [2:0]axi4in_axi_arprot;
wire [3:0]axi4in_axi_arregion;
wire [3:0]axi4in_axi_arqos;
wire axi4in_axi_arvalid;
wire axi4in_axi_arready;
wire [31:0]axi4in_axi_rdata;
wire [1:0]axi4in_axi_rresp;
wire axi4in_axi_rlast;
wire axi4in_axi_rvalid;
wire axi4in_axi_rready;
// AXI4 to AXI4-Lite Protocol converter output
wire [31:0]SDCin_axi_awaddr;
wire [7:0]SDCin_axi_awlen;
wire [2:0]SDCin_axi_awsize;
wire [1:0]SDCin_axi_awburst;
wire [0:0]SDCin_axi_awlock;
wire [3:0]SDCin_axi_awcache;
wire [2:0]SDCin_axi_awprot;
wire [3:0]SDCin_axi_awregion;
wire [3:0]SDCin_axi_awqos;
wire SDCin_axi_awvalid;
wire SDCin_axi_awready;
wire [31:0]SDCin_axi_wdata;
wire [3:0]SDCin_axi_wstrb;
wire SDCin_axi_wlast;
wire SDCin_axi_wvalid;
wire SDCin_axi_wready;
wire [1:0]SDCin_axi_bresp;
wire SDCin_axi_bvalid;
wire SDCin_axi_bready;
wire [31:0]SDCin_axi_araddr;
wire [7:0]SDCin_axi_arlen;
wire [2:0]SDCin_axi_arsize;
wire [1:0]SDCin_axi_arburst;
wire [0:0]SDCin_axi_arlock;
wire [3:0]SDCin_axi_arcache;
wire [2:0]SDCin_axi_arprot;
wire [3:0]SDCin_axi_arregion;
wire [3:0]SDCin_axi_arqos;
wire SDCin_axi_arvalid;
wire SDCin_axi_arready;
wire [31:0]SDCin_axi_rdata;
wire [1:0]SDCin_axi_rresp;
wire SDCin_axi_rlast;
wire SDCin_axi_rvalid;
wire SDCin_axi_rready;
// ----------------------------------------------------------------
@ -408,6 +429,14 @@ module fpgaTop
end
endgenerate
// IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t));
// IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t));
// reset controller XILINX IP
xlnx_proc_sys_reset xlnx_proc_sys_reset_0
(.slowest_sync_clk(CPUCLK),
@ -514,7 +543,7 @@ module fpgaTop
.aresetn(peripheral_aresetn),
// Connect Masters
.s_axi_awid({m_axi_awid, m01_axi_awid}),
.s_axi_awid({m_axi_awid, 8'b0}),
.s_axi_awaddr({m_axi_awaddr, m01_axi_awaddr}),
.s_axi_awlen({m_axi_awlen, m01_axi_awlen}),
.s_axi_awsize({m_axi_awsize, m01_axi_awsize}),
@ -534,7 +563,7 @@ module fpgaTop
.s_axi_bresp({m_axi_bresp, m01_axi_bresp}),
.s_axi_bvalid({m_axi_bvalid, m01_axi_bvalid}),
.s_axi_bready({m_axi_bready, m01_axi_bready}),
.s_axi_arid({m_axi_arid, m01_axi_arid}),
.s_axi_arid({m_axi_arid, 8'b0}),
.s_axi_araddr({m_axi_araddr, m01_axi_araddr}),
.s_axi_arlen({m_axi_arlen, m01_axi_arlen}),
.s_axi_arsize({m_axi_arsize, m01_axi_arsize}),
@ -570,7 +599,7 @@ module fpgaTop
.m_axi_wlast({s00_axi_wlast, s01_axi_wlast}),
.m_axi_wvalid({s00_axi_wvalid, s01_axi_wvalid}),
.m_axi_wready({s00_axi_wready, s01_axi_wready}),
.m_axi_bid({s00_axi_bid, s01_axi_bid}),
.m_axi_bid({s00_axi_bid, 8'b0}),
.m_axi_bresp({s00_axi_bresp, s01_axi_bresp}),
.m_axi_bvalid({s00_axi_bvalid, s01_axi_bvalid}),
.m_axi_bready({s00_axi_bready, s01_axi_bready}),
@ -586,7 +615,7 @@ module fpgaTop
.m_axi_araddr({s00_axi_araddr, s01_axi_araddr}),
.m_axi_arlock({s00_axi_arlock, s01_axi_arlock}),
.m_axi_arready({s00_axi_arready, s01_axi_arready}),
.m_axi_rid({s00_axi_rid, s01_axi_rid}),
.m_axi_rid({s00_axi_rid, 8'b0}),
.m_axi_rdata({s00_axi_rdata, s01_axi_rdata}),
.m_axi_rresp({s00_axi_rresp, s01_axi_rresp}),
.m_axi_rvalid({s00_axi_rvalid, s01_axi_rvalid}),
@ -645,42 +674,107 @@ module fpgaTop
.s_axi_rready(s01_axi_rready),
// Master interface
.m_axi_awaddr(SDCin_axi_awaddr),
.m_axi_awlen(SDCin_axi_awlen),
.m_axi_awsize(SDCin_axi_awsize),
.m_axi_awburst(SDCin_axi_awburst),
.m_axi_awlock(SDCin_axi_awlock),
.m_axi_awcache(SDCin_axi_awcache),
.m_axi_awprot(SDCin_axi_awprot),
.m_axi_awregion(SDCin_axi_awregion),
.m_axi_awqos(SDCin_axi_awqos),
.m_axi_awvalid(SDCin_axi_awvalid),
.m_axi_awready(SDCin_axi_awready),
.m_axi_wdata(SDCin_axi_wdata),
.m_axi_wstrb(SDCin_axi_wstrb),
.m_axi_wlast(SDCin_axi_wlast),
.m_axi_wvalid(SDCin_axi_wvalid),
.m_axi_wready(SDCin_axi_wready),
.m_axi_bresp(SDCin_axi_bresp),
.m_axi_bvalid(SDCin_axi_bvalid),
.m_axi_bready(SDCin_axi_bready),
.m_axi_araddr(SDCin_axi_araddr),
.m_axi_arlen(SDCin_axi_arlen),
.m_axi_arsize(SDCin_axi_arsize),
.m_axi_arburst(SDCin_axi_arburst),
.m_axi_arlock(SDCin_axi_arlock),
.m_axi_arcache(SDCin_axi_arcache),
.m_axi_arprot(SDCin_axi_arprot),
.m_axi_arregion(SDCin_axi_arregion),
.m_axi_arqos(SDCin_axi_arqos),
.m_axi_arvalid(SDCin_axi_arvalid),
.m_axi_arready(SDCin_axi_arready),
.m_axi_rdata(SDCin_axi_rdata),
.m_axi_rresp(SDCin_axi_rresp),
.m_axi_rlast(SDCin_axi_rlast),
.m_axi_rvalid(SDCin_axi_rvalid),
.m_axi_rready(SDCin_axi_rready)
.m_axi_awaddr(axi4in_axi_awaddr),
.m_axi_awlen(axi4in_axi_awlen),
.m_axi_awsize(axi4in_axi_awsize),
.m_axi_awburst(axi4in_axi_awburst),
.m_axi_awlock(axi4in_axi_awlock),
.m_axi_awcache(axi4in_axi_awcache),
.m_axi_awprot(axi4in_axi_awprot),
.m_axi_awregion(axi4in_axi_awregion),
.m_axi_awqos(axi4in_axi_awqos),
.m_axi_awvalid(axi4in_axi_awvalid),
.m_axi_awready(axi4in_axi_awready),
.m_axi_wdata(axi4in_axi_wdata),
.m_axi_wstrb(axi4in_axi_wstrb),
.m_axi_wlast(axi4in_axi_wlast),
.m_axi_wvalid(axi4in_axi_wvalid),
.m_axi_wready(axi4in_axi_wready),
.m_axi_bresp(axi4in_axi_bresp),
.m_axi_bvalid(axi4in_axi_bvalid),
.m_axi_bready(axi4in_axi_bready),
.m_axi_araddr(axi4in_axi_araddr),
.m_axi_arlen(axi4in_axi_arlen),
.m_axi_arsize(axi4in_axi_arsize),
.m_axi_arburst(axi4in_axi_arburst),
.m_axi_arlock(axi4in_axi_arlock),
.m_axi_arcache(axi4in_axi_arcache),
.m_axi_arprot(axi4in_axi_arprot),
.m_axi_arregion(axi4in_axi_arregion),
.m_axi_arqos(axi4in_axi_arqos),
.m_axi_arvalid(axi4in_axi_arvalid),
.m_axi_arready(axi4in_axi_arready),
.m_axi_rdata(axi4in_axi_rdata),
.m_axi_rresp(axi4in_axi_rresp),
.m_axi_rlast(axi4in_axi_rlast),
.m_axi_rvalid(axi4in_axi_rvalid),
.m_axi_rready(axi4in_axi_rready)
);
xlnx_axi_prtcl_conv axi4tolite
(.aclk(CPUCLK),
.aresetn(peripheral_aresetn),
// AXI4 In
.s_axi_awaddr(axi4in_axi_awaddr),
.s_axi_awlen(axi4in_axi_awlen),
.s_axi_awsize(axi4in_axi_awsize),
.s_axi_awburst(axi4in_axi_awburst),
.s_axi_awlock(axi4in_axi_awlock),
.s_axi_awcache(axi4in_axi_awcache),
.s_axi_awprot(axi4in_axi_awprot),
.s_axi_awregion(axi4in_axi_awregion),
.s_axi_awqos(axi4in_axi_awqos),
.s_axi_awvalid(axi4in_axi_awvalid),
.s_axi_awready(axi4in_axi_awready),
.s_axi_wdata(axi4in_axi_wdata),
.s_axi_wstrb(axi4in_axi_wstrb),
.s_axi_wlast(axi4in_axi_wlast),
.s_axi_wvalid(axi4in_axi_wvalid),
.s_axi_wready(axi4in_axi_wready),
.s_axi_bresp(axi4in_axi_bresp),
.s_axi_bvalid(axi4in_axi_bvalid),
.s_axi_bready(axi4in_axi_bready),
.s_axi_araddr(axi4in_axi_araddr),
.s_axi_arlen(axi4in_axi_arlen),
.s_axi_arsize(axi4in_axi_arsize),
.s_axi_arburst(axi4in_axi_arburst),
.s_axi_arlock(axi4in_axi_arlock),
.s_axi_arcache(axi4in_axi_arcache),
.s_axi_arprot(axi4in_axi_arprot),
.s_axi_arregion(axi4in_axi_arregion),
.s_axi_arqos(axi4in_axi_arqos),
.s_axi_arvalid(axi4in_axi_arvalid),
.s_axi_arready(axi4in_axi_arready),
.s_axi_rdata(axi4in_axi_rdata),
.s_axi_rresp(axi4in_axi_rresp),
.s_axi_rlast(axi4in_axi_rlast),
.s_axi_rvalid(axi4in_axi_rvalid),
.s_axi_rready(axi4in_axi_rready),
// AXI4Lite Out
.m_axi_awaddr(SDCin_axi_awaddr),
.m_axi_awprot(SDCin_axi_awprot),
.m_axi_awvalid(SDCin_axi_awvalid),
.m_axi_awready(SDCin_axi_awready),
.m_axi_wdata(SDCin_axi_wdata),
.m_axi_wstrb(SDCin_axi_wstrb),
.m_axi_wvalid(SDCin_axi_wvalid),
.m_axi_wready(SDCin_axi_wready),
.m_axi_bresp(SDCin_axi_bresp),
.m_axi_bvalid(SDCin_axi_bvalid),
.m_axi_bready(SDCin_axi_bready),
.m_axi_araddr(SDCin_axi_araddr),
.m_axi_arprot(SDCin_axi_arprot),
.m_axi_arvalid(SDCin_axi_arvalid),
.m_axi_arready(SDCin_axi_arready),
.m_axi_rdata(SDCin_axi_rdata),
.m_axi_rresp(SDCin_axi_rresp),
.m_axi_rvalid(SDCin_axi_rvalid),
.m_axi_rready(SDCin_axi_rready)
);
sdc_controller axiSDC
(.clock(CPUCLK),
@ -724,13 +818,15 @@ module fpgaTop
.m_axi_rlast(SDCout_axi_rlast),
.m_axi_rresp(SDCout_axi_rresp),
.m_axi_rvalid(SDCout_axi_rvalid),
.m_axi_rready(SDCout_axi_rready)
.m_axi_rready(SDCout_axi_rready),
// SDC interface
//.sdio_cmd(SDCcmd),
//.sdio_dat(SDCdat),
//.sdio_cd()
//.sdio_cmd(1'b0),
//.sdio_dat(4'b0),
//.sdio_cd(1'b0)
.sd_dat_i(4'b0),
.sd_cmd_i(1'b0)
);
@ -771,7 +867,7 @@ module fpgaTop
.s_axi_arvalid(SDCout_axi_arvalid),
.s_axi_arready(SDCout_axi_arready),
.s_axi_rdata(SDCout_axi_rdata),
//.s_axi_rresp(),
.s_axi_rresp(SDCout_axi_rresp),
.s_axi_rlast(SDCout_axi_rlast),
.s_axi_rvalid(SDCout_axi_rvalid),
.s_axi_rready(SDCout_axi_rready),

118
pipelined/src/uncore/newsdc/axi_sdc_controller.v
View File

@ -37,101 +37,109 @@ module sdc_controller #(
parameter voltage_controll_reg = 3300,
parameter capabilies_reg = 16'b0000_0000_0000_0011
) (
input wire async_resetn,
input wire async_resetn,
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK" *)
(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF M_AXI:S_AXI_LITE, FREQ_HZ 100000000" *)
input wire clock,
input wire clock,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *)
(* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32" *)
input wire [15:0] s_axi_awaddr,
input wire [15:0] s_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *)
input wire s_axi_awvalid,
input wire s_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *)
output wire s_axi_awready,
output wire s_axi_awready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *)
input wire [31:0] s_axi_wdata,
input wire [31:0] s_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *)
input wire s_axi_wvalid,
input wire s_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *)
output wire s_axi_wready,
output wire s_axi_wready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *)
output reg [1:0] s_axi_bresp,
output reg [1:0] s_axi_bresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *)
output reg s_axi_bvalid,
output reg s_axi_bvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *)
input wire s_axi_bready,
input wire s_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *)
input wire [15:0] s_axi_araddr,
input wire [15:0] s_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *)
input wire s_axi_arvalid,
input wire s_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *)
output wire s_axi_arready,
output wire s_axi_arready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *)
output reg [31:0] s_axi_rdata,
output reg [31:0] s_axi_rdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *)
output reg [1:0] s_axi_rresp,
output reg [1:0] s_axi_rresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *)
output reg s_axi_rvalid,
output reg s_axi_rvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *)
input wire s_axi_rready,
input wire s_axi_rready,
(* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4, DATA_WIDTH 32" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output reg [dma_addr_bits-1:0] m_axi_awaddr,
output reg [dma_addr_bits-1:0] m_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output reg [7:0] m_axi_awlen,
output reg [7:0] m_axi_awlen,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output reg m_axi_awvalid,
output reg m_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready,
input wire m_axi_awready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31:0] m_axi_wdata,
output wire [31:0] m_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output reg m_axi_wlast,
output reg m_axi_wlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output reg m_axi_wvalid,
output reg m_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready,
input wire m_axi_wready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1:0] m_axi_bresp,
input wire [1:0] m_axi_bresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid,
input wire m_axi_bvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready,
output wire m_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output reg [dma_addr_bits-1:0] m_axi_araddr,
output reg [dma_addr_bits-1:0] m_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output reg [7:0] m_axi_arlen,
output reg [7:0] m_axi_arlen,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output reg m_axi_arvalid,
output reg m_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready,
input wire m_axi_arready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31:0] m_axi_rdata,
input wire [31:0] m_axi_rdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast,
input wire m_axi_rlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1:0] m_axi_rresp,
input wire [1:0] m_axi_rresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid,
input wire m_axi_rvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready,
output wire m_axi_rready,
// SD BUS
inout wire sdio_cmd,
inout wire [3:0] sdio_dat,
//inout wire sdio_cmd,
//inout wire [3:0] sdio_dat,
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 sdio_clk CLK" *)
(* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *)
output reg sdio_clk,
output reg sdio_clk,
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sdio_reset RST" *)
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
output reg sdio_reset,
input wire sdio_cd,
output reg sdio_reset,
input wire sdio_cd,
output reg sd_dat_reg_t,
output reg [3:0] sd_dat_reg_o,
input wire [3:0] sd_dat_i,
output reg sd_cmd_reg_t,
output reg sd_cmd_reg_o,
input wire sd_cmd_i,
// Interrupts
output wire interrupt
output wire interrupt
);
`include "sd_defines.h"
@ -240,22 +248,22 @@ end
// ------ SD IO Buffers
wire sd_cmd_i;
// wire sd_cmd_i;
wire sd_cmd_o;
wire sd_cmd_oe;
reg sd_cmd_reg_o;
reg sd_cmd_reg_t;
wire [3:0] sd_dat_i;
// reg sd_cmd_reg_o;
// reg sd_cmd_reg_t;
// wire [3:0] sd_dat_i;
wire [3:0] sd_dat_o;
wire sd_dat_oe;
reg [3:0] sd_dat_reg_o;
reg sd_dat_reg_t;
// reg [3:0] sd_dat_reg_o;
// reg sd_dat_reg_t;
IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t));
IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t));
IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t));
IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t));
IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t));
// IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t));
// IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t));
always @(negedge clock) begin
// Output data delayed by 1/2 clock cycle (5ns) to ensure

40
tests/custom/boot/boot.c
View File

@ -369,6 +369,46 @@ static int ini_sd(void) {
return 0;
}
DRESULT disk_read(BYTE drv, BYTE * buf, LBA_t sector, UINT count) {
if (!count) return RES_PARERR;
if (drv_status & STA_NOINIT) return RES_NOTRDY;
/* Convert LBA to byte address if needed */
if (!(card_type & CT_BLOCK)) sector *= 512;
while (count > 0) {
UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count;
unsigned bytes = bcnt * 512;
if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR;
if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return RES_ERROR;
sector += (card_type & CT_BLOCK) ? bcnt : bytes;
count -= bcnt;
buf += bytes;
}
return RES_OK;
}
void disk_read(BYTE drv, BYTE * buf, LBA_t sector, UINT count) {
if (!count) return RES_PARERR;
if (drv_status & STA_NOINIT) return RES_NOTRDY;
/* Convert LBA to byte address if needed */
if (!(card_type & CT_BLOCK)) sector *= 512;
while (count > 0) {
UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count;
unsigned bytes = bcnt * 512;
if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR;
if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return RES_ERROR;
sector += (card_type & CT_BLOCK) ? bcnt : bytes;
count -= bcnt;
buf += bytes;
}
return RES_OK;
}
int main() {
ini_sd();