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Added the rest of the tests lited in Chapter 5 test plan

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Kip Macsai-Goren 2022-04-17 20:53:37 +00:00
parent 5a6ad32688
commit 1af47c9d25
12 changed files with 4356 additions and 74 deletions
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1024
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MIE-01.reference_output Normal file
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tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PIE-stack-01.reference_output Normal file
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tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output
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00000aaa # Test 5.3.1.5: readback value of SIE after enabling all interrupts.
00000000
00000007 # mcause from m time interrupt
80000000
00000000 # mtval for mtime interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
0000000b # mcause from M mode ecall from test termination
00000000
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
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00000aaa # Test 5.3.1.5: readback value of MIE after enabling all interrupts.
00000000
00000222 # readback value of mideleg after attempting to delegate all interrupts.
00000000
0000000b # mcause from ecall for going from M mode to S mode
00000000
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000001 # mcause from s soft interrupt
80000000
00000000 # mtval for ssoft interrupt (0x0)
00000000
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000009 # mcause from ecall for going from S mode to M mode
00000000
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
0000000b # mcause from ecall for going from M mode to U mode
00000000
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000001 # mcause from s soft interrupt from user mode this time
80000000
00000000 # mtval for mtime interrupt (0x0)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000008 # mcause from U mode ecall from test termination
00000000
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00000000 # masked out mstatus.MPP = 00, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
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tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-sret-01.reference_output Normal file
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tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S Normal file
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///////////////////////////////////////////
//
// WALLY-MIE
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1.
WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR.
// test 5.3.1.6 Interrupt enabling and priority tests
// note that none of these interrupts should be caught or handled.
jal cause_m_soft_interrupt
END_TESTS
TEST_STACK_AND_DATA

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tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-01.S Normal file
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///////////////////////////////////////////
//
// WALLY-privilege-interrupt-enable-stack
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1
WRITE_READ_CSR mie, 0xFFF
// test 5.3.1.6 Interrupt enabling and priority tests
// Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling
jal cause_m_soft_interrupt
li x28, 0x8
csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen
// attempt to cause interrupt, it should not go through
jal cause_m_soft_interrupt
END_TESTS
TEST_STACK_AND_DATA

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tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-s-01.S Normal file
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///////////////////////////////////////////
//
// WALLY-privilege-interrupt-enable-stack
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1 // necessary so we can go to S mode
TRAP_HANDLER s, DEBUG=1 // neccessary to handle s mode interrupts.
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1
WRITE_READ_CSR mie, 0xFFF // enable all interrupts, including supervisor ones
WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode.
// test 5.3.1.6 Interrupt enabling and priority tests
GOTO_S_MODE
// Cause interrupt, ensuring that status.sie = 0 , status.spie = 1, and status.spp = 1 during trap handling
jal cause_s_soft_interrupt
li x28, 0x2
csrc sstatus, x28 // set sstatus.SIE bit to 0. interrupts from S mode should not happen
// attempt to cause interrupt, it should not go through
jal cause_s_soft_interrupt
END_TESTS
TEST_STACK_AND_DATA

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tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S
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INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.5 Unvectored interrupt tests
TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
li x28, 0x8
csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
csrs mstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
WRITE_READ_CSR mie, 0xFFF
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
// *** this assumes that interrupt code 0 remains reserved
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
jal cause_m_time_interrupt
END_TESTS

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INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.5 Unvectored interrupt tests
TRAP_HANDLER m, VECTORED=0, DEBUG=1 // necessary to handle changing modes
TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
// li x28, 0x8
// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1
WRITE_READ_CSR mie, 0xFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
GOTO_S_MODE
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
// *** this assumes that interrupt code 0 remains reserved
jal cause_s_soft_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
GOTO_M_MODE
GOTO_U_MODE
jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
GOTO_U_MODE // Should cause software interrupt to fire off.
END_TESTS

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///////////////////////////////////////////
//
// WALLY-trap-sret
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
TRAP_HANDLER m, DEBUG=1
// test 5.3.1.6 Interrupt enabling and priority tests
li x28, 0x400000
csrs mstatus, x28 // Set mstatus.tsr to 1.
GOTO_S_MODE
sret // attempt to run sret instruction.
// should cause illegal instruction exception despite being in s mode
END_TESTS
TEST_STACK_AND_DATA