Jordan Carlin
f6b0805fd4
More lint cleanup: remove unused params
2024-11-16 12:35:37 -08:00
Rose Thompson
e22f30ec14
Better name for CacheSetTag2.
2024-11-13 12:24:35 -06:00
Rose Thompson
8fb1673ab3
Updated email address authorship for my files.
2024-10-15 10:27:53 -05:00
David Harris
c1fd7a9589
Removed unused signals
2024-06-18 07:28:52 -07:00
David Harris
2fc9edff45
Fixed Issue #752 of Verilator simulation by changing LRUMemory to be nonblocking now that Verilator handles this construct properly
2024-06-18 04:40:38 -07:00
David Harris
8f09240e6c
Simplified outdated documentation pointers
2024-06-14 03:42:15 -07:00
Rose Thompson
b45b7ff7d6
Signal name changes to match book.
2024-06-02 16:32:25 -05:00
Rose Thompson
273b41df99
Changed name of cache parameter NUMLINES to NUMSETS to better match book.
2024-05-28 17:55:43 -05:00
David Harris
3f195884e9
Defined bit sizes more precisely to help VCS lint and conform to coding style
2024-04-21 08:40:11 -07:00
Rose Thompson
5b4d3f49b0
Fixed #689 caused by removal of #1 delays. For some reason the #1 were not removed from cacheLRU.sv.
2024-03-26 12:26:03 -05:00
David Harris
c7c12cc3a8
Fixed Lint issue on cacheLRU
2024-03-06 14:00:57 -08:00
Rose Thompson
0d8c251fa4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-03-06 15:35:34 -06:00
David Harris
b386331cc8
Changed '0 to 0 where possible per Chapter 4 style guidelines
2024-03-06 05:48:17 -08:00
Rose Thompson
c093f53c9c
Merge branch 'main' of https://github.com/openhwgroup/cvw
...
Cleaned up the cacheLRU.
2024-03-05 11:08:40 -06:00
Rose Thompson
e8e0538f6c
Changed to non-blocking in cacheLRU and removed clearing LRU bits on flush.
2024-03-05 10:33:47 -06:00
Rose Thompson
457d3481e7
How did this error get past for so long.
2024-03-04 17:58:41 -06:00
Rose Thompson
0222e8f42a
Don't want to clear the lru bits on invalidation (clearvalid).
2024-03-04 17:52:41 -06:00
Rose Thompson
85691f0e8b
Simplified and clarified names in cacheLRU.
2024-02-29 17:18:01 -06:00
David Harris
90e89ced1d
Fixes for synthesis. HPTW change will break x detection
2024-02-26 04:20:08 -08:00
David Harris
66c1c71a56
Coverage improvements
2024-02-04 18:56:40 -08:00
David Harris
0abfe5cb55
Fixed some lint errors in derived configs
2024-01-31 11:39:59 -08:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
Rose Thompson
f592baa741
Closer.
2023-12-13 18:15:32 -06:00
Rose Thompson
13bb5d845b
On the way to solving the store delay hazard.
2023-12-13 10:39:01 -06:00
David Harris
f89fd8a7fe
removed unused cache signals
2023-11-20 23:16:35 -08:00
David Harris
6e7c0547a1
Modified log2 coding to avoid synthesis warning
2023-10-19 11:16:02 -07:00
Ross Thompson
9f37fef145
The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush.
2023-08-14 16:39:18 -05:00
Ross Thompson
85567841eb
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
75b5c23edd
Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
2023-06-15 14:05:44 -05:00
Harshini Srinath
e7fb7403ef
Update cacheLRU.sv
...
Code clean up
2023-06-09 08:43:38 -07:00
Ross Thompson
7c0eb16e62
Fixed bug in cacheLRU when NUMWAYS = 2.
2023-04-27 14:30:01 -05:00
Ross Thompson
30e3d2cdce
Merge pull request #233 from AlecVercruysse/coverage3
...
Full I$ coverage
2023-04-14 22:15:11 -05:00
Limnanthes Serafini
0b6ce1b031
Some cleanup
2023-04-13 21:01:57 -07:00
Alec Vercruysse
a1bbcd5e8a
Coverage and readability improvements to LRUUpdate logic
...
The genvar stuff was switched to readable names to make it easier
to understand for the first time. In the LRUUpdate logic for loop,
a special case was added for simpler logic in the case of the root
node, to hit coverage.
2023-04-12 01:15:35 -07:00
Alec Vercruysse
7c9f68e984
Remove FlushStage Logic from CacheLRU
...
For coverage.
LRUWriteEn is gated by FlushStage in cache.sv,
so removing the signal completely avoids future confusion.
Update cache.sv to reflect cacheLRU edit.
2023-04-12 01:15:35 -07:00
Alec Vercruysse
9df246e5de
put cacheLRU coverage explanation on another line
...
the `: explanation` syntax was not working
2023-04-05 11:48:18 -07:00
Alec Vercruysse
af113c7268
Exclude CacheLRU log2 function from coverage
2023-04-05 11:48:18 -07:00
Alec Vercruysse
d507f85190
icache coverage improvements by simplifying logic
2023-03-29 13:04:00 -07:00
Ross Thompson
c190444fa2
Updated CAdr to CacheSet.
2023-03-13 14:53:00 -05:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
