David Harris
|
f68b9c224a
|
Fixed WALLY-trap test case to use menvcfg
|
2023-06-09 15:24:26 -07:00 |
|
David Harris
|
b70b0c7c5e
|
Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
|
2023-06-09 14:40:01 -07:00 |
|
David Harris
|
19096a812a
|
Added Zifencei ISA to tests where necessary to support new compiler
|
2023-05-16 11:18:27 -07:00 |
|
David Harris
|
0a7a159d69
|
Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile
|
2023-05-14 06:58:29 -07:00 |
|
Kip Macsai-Goren
|
34200e8c76
|
restored original virt mem tests when svadu is not supported
|
2023-04-11 18:47:08 -07:00 |
|
Kip Macsai-Goren
|
c4766c8a02
|
renamed virt mem tests to include svadu
|
2023-04-11 18:46:37 -07:00 |
|
Kip Macsai-Goren
|
b2d6084eea
|
removed unnecessary 'deadbeef's at the end of reference outputs
|
2023-04-11 18:32:04 -07:00 |
|
Kip Macsai-Goren
|
a82c0a7780
|
Modified virt mem tests to do correct r/w when svadu is enabled
|
2023-04-11 18:08:30 -07:00 |
|
Kip Macsai-Goren
|
e0b938b409
|
Removed Trap outputs from writes covered by SVADU
|
2023-04-11 17:41:57 -07:00 |
|
Kip Macsai-Goren
|
a899606c2b
|
Removed Sail from virt mem tests due to sail not recognizing SVADU
|
2023-04-11 17:41:31 -07:00 |
|
Kip Macsai-Goren
|
19305fe60a
|
Added sail simulation to priv tests that support it
|
2023-04-11 13:26:59 -07:00 |
|
Kip Macsai-Goren
|
a7c9d3d37b
|
ported medelg fixes to 32 bit tests. Requires a make allclean
|
2023-03-29 16:31:28 -07:00 |
|
David Harris
|
2e5c50e24a
|
Fixed RV32 tests after PMP fix
|
2023-03-28 08:35:23 -07:00 |
|
David Harris
|
e8904411ce
|
Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
|
2023-03-28 06:58:17 -07:00 |
|
Kip Macsai-Goren
|
758da62a9f
|
ported fixes to 32 bit tests
|
2023-03-24 11:22:39 -07:00 |
|
Kip Macsai-Goren
|
db6caedfec
|
added in the CSR name for stimecmp(h)
|
2023-03-04 15:53:03 -08:00 |
|
Kip Macsai-Goren
|
ab6b953a4b
|
removed changes to counteren from stimecmp tests
|
2023-03-04 15:46:57 -08:00 |
|
Kip Macsai-Goren
|
ac5c53a870
|
Added correct causing and handling of S time interrupts to test suite.
|
2023-03-04 15:04:17 -08:00 |
|
David Harris
|
f0c0111ab0
|
Renamed section 12.3 to 8.3 in MMU test definitions
|
2023-02-19 05:46:46 -08:00 |
|
David Harris
|
4883351bd2
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-01-28 18:18:53 -08:00 |
|
Kip Macsai-Goren
|
ee1bcf62ee
|
Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts.
|
2023-01-28 17:29:35 -08:00 |
|
David Harris
|
2af94bf283
|
Removed unused reference files
|
2023-01-27 07:21:55 -08:00 |
|
Kip Macsai-Goren
|
964084f0b3
|
added fs=00 to status fp enabled test
|
2022-12-22 15:15:53 -08:00 |
|
Kip Macsai-Goren
|
d25d699800
|
Added status.tvm bit test that passes make and regression
|
2022-12-22 14:43:22 -08:00 |
|
Kip Macsai-Goren
|
a37bde7452
|
updated trap handler alignemnts to 64 bytes in priv tests
|
2022-12-22 14:23:04 -08:00 |
|
David Harris
|
ca949f2110
|
Only delegated bits of SIP are readable
|
2022-12-21 12:32:49 -08:00 |
|
Ross Thompson
|
f6393d1288
|
Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
|
2022-12-21 13:16:09 -06:00 |
|
Ross Thompson
|
c41d58bd29
|
Vectored interrupts now require 64 byte alignment.
Eliminates adder.
|
2022-12-21 12:05:49 -06:00 |
|
Kip Macsai-Goren
|
4c81b6fa5f
|
added corrrect scr read out of uart to periph test
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
51e78d9e48
|
added copies of 64 bit tests to 32 bit periph and priv tests
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
540d6c2f41
|
added -01 to all WALLY tests
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
21e045eb7d
|
added potential fix to overrun error and fifo interrupt error. test passes
|
2022-11-06 22:01:02 -08:00 |
|
Kip Macsai-Goren
|
90ef371abc
|
fixed fifo timout handling. error now in data ready interrupt
|
2022-11-05 13:34:24 -07:00 |
|
Kip Macsai-Goren
|
c06da6e6fe
|
fixed broken instructions so make works.
|
2022-11-03 23:06:20 +00:00 |
|
Ross Thompson
|
103514a8e0
|
More outline for uart timeout interrupt.
|
2022-10-28 13:53:56 -05:00 |
|
Ross Thompson
|
21eca47d2e
|
Untested change to uart test for outline of how to handle rx fifo timeout.
|
2022-10-28 13:31:16 -05:00 |
|
Kip Macsai-Goren
|
6e45698b86
|
Added test for UART FIFO timeout. Does not pass regression
|
2022-10-25 05:35:56 +00:00 |
|
Kip Macsai-Goren
|
c18c181fc0
|
fixed endianness mstatush problem, passes make, not regression
|
2022-10-04 17:37:39 +00:00 |
|
Kip Macsai-Goren
|
e603973dff
|
added xlen and endianness test edits. xlen passes but endinanness still won't make
|
2022-09-26 05:03:19 +00:00 |
|
Kip Macsai-Goren
|
0cc7f5719c
|
ported endianness tests to 32 bits (not tested in regression yet)
|
2022-09-18 00:10:29 +00:00 |
|
David Harris
|
898dbc8e74
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
|
2022-08-03 09:33:56 -07:00 |
|
David Harris
|
4fb467ee8a
|
Debugging plic-s test
|
2022-08-03 13:21:09 +00:00 |
|
David Harris
|
7e5b78f240
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
cab0349701
|
Started plic-s tests
|
2022-08-03 03:48:08 +00:00 |
|
David Harris
|
93d7d7179e
|
Added parity and stop bit tests to UART
|
2022-07-28 04:35:51 +00:00 |
|
David Harris
|
429bdae1c4
|
Fixed UART reference output
|
2022-07-27 22:16:38 +00:00 |
|
David Harris
|
b08c87cb47
|
Finished UART test
|
2022-07-27 04:06:59 +00:00 |
|
slmnemo
|
7348af7fd5
|
Updated reference file for UART test
|
2022-07-26 09:39:31 -07:00 |
|
slmnemo
|
5218865a7f
|
Committing changes made to UART test
|
2022-07-26 09:14:40 -07:00 |
|
slmnemo
|
bfced6bfe8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-22 17:13:38 -07:00 |
|