bbracker
df51d9908d
AHB bugfixes and sim waveview refactoring
2021-03-18 18:25:12 -04:00
Shreya Sanghai
dfc86539cc
Merge branch 'gshare' into main
...
Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Ross Thompson
181a28e875
Fixed minor bug with the size of gshare.
2021-03-18 16:00:09 -05:00
Teo Ene
0ff785549e
Switched coremark to RV64IM
2021-03-17 22:39:56 -05:00
Teo Ene
29634f1475
Temporarily reverted my last few commits
2021-03-17 15:16:01 -05:00
Teo Ene
e6661ea26a
fix to last commit
2021-03-17 15:07:02 -05:00
Teo Ene
083a24c06b
addition to last commit
2021-03-17 14:52:31 -05:00
Elizabeth Hedenberg
bccd37d778
fixing coremark branch prediction
2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
a3b2ffb2c9
Merge branch '3_3_2021' into main
...
Making sure coremark works with spring break changes
2021-03-17 14:11:37 -04:00
Ross Thompson
7bc95ba073
Fixed issue with sim-wally-batch. Are people still using this script?
2021-03-17 11:17:52 -05:00
Ross Thompson
0e2352a6de
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-17 11:07:57 -05:00
Ross Thompson
31ad619a21
Added possibly working OSU test bench as a precursor to running a bp benchmark.
...
Fixed a few bugs with the function radix.
2021-03-17 11:06:32 -05:00
Jarred Allen
ed68d8240b
Undo accidental change
2021-03-16 18:16:00 -04:00
Jarred Allen
ba7bfa9056
Condense the parallel and non-parallel wally-pipelined-batch.do files into one
2021-03-16 18:15:13 -04:00
Jarred Allen
6e7fc07fcf
Change busybear to only check that first 100k instructions load
2021-03-16 17:43:39 -04:00
Noah Boorstin
cd58f8a12d
remove regression-wally.sh
2021-03-15 19:03:57 -04:00
Ross Thompson
8e51935082
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Ross Thompson
d341e2d5cb
Fixed the parallel script so the rv64ic passes.
...
rv32ic and busybear still have issues.
2021-03-15 12:04:59 -05:00
Ross Thompson
0edaa625e3
Fixed the issue with the batch mode not working after adding the function radix.
2021-03-12 20:16:03 -06:00
Ross Thompson
ccaaa829ce
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-12 14:58:04 -06:00
Ross Thompson
0637874cac
Cleanup of the branch predictor flush and stall controls.
2021-03-12 14:57:53 -06:00
Ross Thompson
b1d1f3995c
Improve version of the function radix which does not cause the wave file rendering to slow down.
2021-03-11 17:12:21 -06:00
Noah Boorstin
be0bd317e9
test regression script: add commented out rv32ic tests
2021-03-11 12:57:54 -05:00
Noah Boorstin
641a320894
add rv32ic regression test
2021-03-11 12:40:29 -05:00
Noah Boorstin
2dfb944d15
test regression script: parallalize better
2021-03-11 12:25:20 -05:00
Noah Boorstin
b13365365b
test regression script: try adding verilator checking also
2021-03-11 07:32:31 +00:00
Noah Boorstin
8717f3604b
try adding delays to test regression script
2021-03-11 06:59:50 +00:00
Noah Boorstin
c5b6ca4cc6
this is just a test for now, try to reimplement regression-wally in bash
2021-03-11 06:45:45 +00:00
Ross Thompson
f1f7884e10
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-10 15:37:02 -06:00
Ross Thompson
149c9aa0f2
Added debug option to disable the function radix if not needed.
...
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 15:17:02 -06:00
Ross Thompson
4d7e926dbb
I finally think I got the function radix debugger working across both 32 and 64 bit applications.
2021-03-10 14:43:44 -06:00
Ross Thompson
7b7cacbaf0
Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.
2021-03-10 11:00:51 -06:00
David Harris
0baa004bb4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-09 09:28:32 -05:00
David Harris
bea8ac6d59
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Noah Boorstin
9274d09ae2
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
Noah Boorstin
08e3691e59
busybear: make a second .do file with better optimization for command line mode
2021-03-08 19:35:00 +00:00
Noah Boorstin
1fc00d41c2
busybear: load mem files from verilog instead of .do
2021-03-08 19:26:26 +00:00
Ross Thompson
a3759f585d
Updated the paths to the branch predictor memory preloads for busy bear.
2021-03-05 15:36:00 -06:00
Ross Thompson
d6bc34121f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-05 15:27:22 -06:00
Ross Thompson
9a93193d6a
Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
2021-03-05 15:23:53 -06:00
Noah Boorstin
d3bf36b15f
busybear: add branch preditor loading to do file
...
(sorry to add more loading to the do instead of less)
2021-03-05 21:01:41 +00:00
Noah Boorstin
f0a103687e
Merge branch 'main' into busybear
2021-03-05 20:27:19 +00:00
Noah Boorstin
6981907521
fix wally-pipelined-batch.do to match wally-pipelined.do
2021-03-05 20:27:01 +00:00
bbracker
420c9a11c2
refactored sim file
2021-03-05 14:25:16 -05:00
bbracker
62dd9e3075
first merge of ahb fix
2021-03-05 14:24:22 -05:00
Noah Boorstin
7208b9bcf2
busybear: better implenetation of sim-busybear-batch
2021-03-05 00:39:03 +00:00
Noah Boorstin
cfcd7d1518
busybear: make imperas tests work again
2021-03-04 22:44:49 +00:00
Noah Boorstin
fde94f9057
Merge branch 'main' into busybear
...
Conflicts:
wally-pipelined/src/uncore/imem.sv
2021-03-04 20:16:03 +00:00
Ross Thompson
619bbd9d83
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Teo Ene
95ce4b7daa
Edited assemby of bare-metal coremark to make it run
2021-03-04 07:45:40 -06:00