David Harris
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d7b016e8f3
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Cleaned up Zicond implementation
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2024-01-12 18:12:52 -08:00 |
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David Harris
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9eb6d9c8b8
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Added Zicond support
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2024-01-11 07:37:15 -08:00 |
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Rose Thompson
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626b89320c
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More cleanup.
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2023-12-29 16:51:39 -06:00 |
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Rose Thompson
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0264a17f77
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Reverted dtim to use store delay stall, but only (load after store).
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2023-12-29 16:06:30 -06:00 |
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Rose Thompson
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fbab9f6c6d
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Updated comments about AMO and CMO stalls.
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2023-12-29 15:31:11 -06:00 |
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David Harris
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2c2f692f3a
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Moved forwarding logic into controller
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2023-12-26 21:17:01 -08:00 |
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David Harris
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6cb4a9e905
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-12-15 19:27:10 -08:00 |
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Rose Thompson
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438451ee02
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Fixed the AMO hazard.
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2023-12-15 11:55:54 -06:00 |
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David Harris
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51b43bffa3
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ALU cleanup
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2023-12-14 19:06:39 -08:00 |
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Rose Thompson
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1ca9a8be6d
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I think I solved the AMO/store hazard issue introduced by removing the store delay hazard.
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2023-12-14 16:31:02 -06:00 |
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Rose Thompson
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a7f0aaa722
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Added comments to finish store delay stall removal.
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2023-12-13 20:35:13 -06:00 |
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Rose Thompson
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f3d43a7713
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Progress on reducing store stall in d cache.
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2023-12-13 15:34:21 -06:00 |
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Rose Thompson
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13bb5d845b
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On the way to solving the store delay hazard.
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2023-12-13 10:39:01 -06:00 |
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Rose Thompson
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80336493f5
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Cleaned up redundant ZICBOM/Z_SUPPORTED.
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2023-11-29 15:20:49 -06:00 |
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Rose Thompson
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69653e5faa
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Fixed minor bug in the cbo hazard logic.
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2023-11-27 23:38:53 -06:00 |
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David Harris
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d3ce683e06
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Removed other unused signals from Verilog
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2023-11-20 23:37:56 -08:00 |
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David Harris
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acc2db256f
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turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep
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2023-11-17 20:25:24 -08:00 |
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David Harris
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434d6b2c5c
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minfo test working again with mconfigptr for RV64
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2023-10-15 06:41:52 -07:00 |
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David Harris
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e75ceb044f
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Improved tlb and controller coverage; fixed exclusions on broken lines
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2023-08-31 00:27:47 -07:00 |
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David Harris
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f7b50f4721
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Preparing to merge with CBO* changes
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2023-08-25 18:41:03 -07:00 |
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Ross Thompson
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21129dde71
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Fixed cbo instruction decode.
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2023-08-18 11:32:30 -05:00 |
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Ross Thompson
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9dcc70d6c1
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Updated the hazard logic for CMO operations.
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2023-08-17 17:58:49 -05:00 |
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Ross Thompson
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12beada55b
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Fixed the privilege decoder bug which prevented the fpga linux boot.
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2023-07-10 17:00:06 -05:00 |
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David Harris
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afe66d0ee4
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Added prefetch instructions; sent cbo instructions to LSU
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2023-07-02 10:55:35 -07:00 |
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David Harris
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723b8266cb
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Added prefetch signals
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2023-07-02 10:06:58 -07:00 |
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David Harris
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482e4e6e92
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Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions
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2023-07-02 09:35:05 -07:00 |
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David Harris
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b6ae5661b4
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Added environment configuration control (menvcfg/senvcfg) of cbo instructions
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2023-07-02 01:52:25 -07:00 |
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David Harris
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15314a9c9a
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Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations
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2023-07-02 00:34:30 -07:00 |
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David Harris
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41e9f20943
|
improved decoder checking atomic and RW and MW and privileged instructions
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2023-07-02 00:02:03 -07:00 |
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David Harris
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e34ef4d636
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improved decoder checking atomic instructions
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2023-07-01 23:10:57 -07:00 |
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David Harris
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d930be332e
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Improved instruction decoding for illegal floating-point loads/stores and fences
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2023-07-01 22:48:04 -07:00 |
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David Harris
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c383407d5c
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Removed redundant and not-covered atomic check from StoreStallD
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2023-06-16 16:05:53 -07:00 |
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Ross Thompson
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4428babda9
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-15 15:38:38 -05:00 |
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Ross Thompson
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85567841eb
|
Merge branch 'testbench-params2'
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2023-06-15 15:31:13 -05:00 |
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David Harris
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9e839988dc
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Gated MDU to save power; doesn't seem to have affected simulation time
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2023-06-15 12:17:23 -07:00 |
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David Harris
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9f88848832
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Bit manipulation comment cleanup
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2023-06-15 12:16:46 -07:00 |
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Ross Thompson
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75b5c23edd
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Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
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2023-06-15 14:05:44 -05:00 |
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David Harris
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a62211bad1
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Gated inputs to BMU when inactive to save power and simulation time
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2023-06-15 11:56:59 -07:00 |
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Ross Thompson
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b8a243827b
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Found a whole bunch of files still using the old `define configurations.
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2023-06-15 13:09:07 -05:00 |
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Ross Thompson
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60e87b08c4
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Improved simulation speed by gating bitmanip zbc's clmul's X and Y inputs with BSelect != 11. Reduced simulation time from 3m45s to 2m35s.
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2023-06-14 15:28:58 -05:00 |
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Harshini Srinath
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5f73c9727f
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Update shifter.sv
Program clean up
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2023-06-12 12:23:45 -07:00 |
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Harshini Srinath
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0f36cbd830
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Update regfile.sv
Program clean up
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2023-06-12 12:21:25 -07:00 |
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Harshini Srinath
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f1cef043c6
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Update ieu.sv
Program clean up
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2023-06-12 12:19:04 -07:00 |
|
Harshini Srinath
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304adcb9b0
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Update extend.sv
Program clean up
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2023-06-12 12:15:33 -07:00 |
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Harshini Srinath
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1d24a9c912
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Update datapath.sv
Program clean up
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2023-06-12 12:13:58 -07:00 |
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Ross Thompson
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052bc95966
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More parameterization. Copied Lim. Still no slow down.
|
2023-05-24 14:49:22 -05:00 |
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Ross Thompson
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b91b54589e
|
Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down.
|
2023-05-24 14:05:44 -05:00 |
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David Harris
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a929656d9a
|
Renamed byteUnit to byteop
|
2023-04-27 14:10:46 -07:00 |
|
Limnanthes Serafini
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b3976daccd
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More cleanup
|
2023-04-13 21:34:50 -07:00 |
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Limnanthes Serafini
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034c289a36
|
Misc typo and indent fixing.
|
2023-04-13 16:54:15 -07:00 |
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