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8,071 Commits 5 Branches 2 Tags 53 MiB
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61 Commits

Author SHA1 Message Date
David Harris
b386331cc8 Changed '0 to 0 where possible per Chapter 4 style guidelines 2024-03-06 05:48:17 -08:00
David Harris
efdc571f59 Removed redundant assertion 2024-02-01 20:14:40 -08:00
David Harris
49714cb282 Fixed assertions to throw fatal error, improved nightly regression to have passing cases 2024-01-31 21:39:18 -08:00
David Harris
74b242ce5c Partial implementation of fcvtmod.w.d; flags disagree in one case where Sail might be wrong, and result 134 is wrong because of overflow 2024-01-17 12:25:06 -08:00
David Harris
da4eca4854 Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int. 2024-01-15 13:24:57 -08:00
David Harris
9eb6d9c8b8 Added Zicond support 2024-01-11 07:37:15 -08:00
Rose Thompson
408bb2c35b Yay! I got verilator to compile our testbench! Does it actually work I don't know. 2023-12-18 16:44:34 -06:00
Rose Thompson
0f7b6ada04 Cleanup. 
Verilator still has issues with riscassertions.sv and the testbench
 2023-12-18 16:38:56 -06:00
Rose Thompson
b7b245fe2f functionName.sv is now linting for rv64gc. 2023-12-18 16:37:26 -06:00
Rose Thompson
c1ac153a4f Closer to verilator support. 2023-12-18 16:26:56 -06:00
Rose Thompson
58942b246b Kind of a frustrating set of changes to get the verilator errors out of the copyShadow module. 2023-12-18 13:34:14 -06:00
Rose Thompson
4a3cc8b9c8 More progress towards verilator. 2023-12-18 13:26:43 -06:00
Rose Thompson
5062a8c89c Added parameter for cache's SRAM length. 
Progress towards verilator support.
 2023-12-18 12:50:49 -06:00
David Harris
aff61ea97a Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator 2023-12-13 11:33:59 -08:00
David Harris
3df4c13daa Updated wallyTracer for Linux boot and wally-batch.do to remove buildroot checkpoint support 2023-11-23 20:36:45 -08:00
David Harris
1f57df7f8b Fixed reference to deleted atomic signal in cache 2023-11-23 20:29:10 -08:00
Rose Thompson
1dac4d221e Disable the trace for normal operation. 2023-11-21 13:49:07 -06:00
Rose Thompson
c77a47b403 Output the instruction trace to the logs directory. 2023-11-21 13:47:58 -06:00
Rose Thompson
b02bd6c835 Finally we got the wally tracer working with linux. 2023-11-21 13:45:55 -06:00
Rose Thompson
3fd6d3464c We are logging now. 2023-11-21 13:02:34 -06:00
Rose Thompson
6ff8d19157 Added code to the wallyTracer to support outputing an instruction trace. 2023-11-21 12:28:19 -06:00
Rose Thompson
bc935b1b3b Fixed second bug in the logger script when branch logging enabled but counter logger not. 2023-11-15 14:56:02 -06:00
Rose Thompson
5d4a89b27c Fixed bug in the btb branch logging. 
We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
 2023-11-15 14:51:47 -06:00
Rose Thompson
540d8d930d Cleanup. 
Linux makefile
wally tracer.  probably reduce some complexity here.
 2023-11-13 14:04:43 -06:00
David Harris
bddd2d573e Shortened path to PCSrcE in logger to avoid problematic hierarchical reference 2023-11-05 07:06:53 -08:00
David Harris
568aa3c4a6 Verilator improvements 2023-11-04 03:21:07 -07:00
David Harris
09aebbf252 Fixed regression error of watchdog timeout when PCM is optimized out of the IFU 2023-11-03 04:38:27 -07:00
Ross Thompson
fc83f33615 Oups. When fixing the linux-imperasdv testbench I accidentally introduced a bug to the tracer. 2023-10-05 13:00:46 -05:00
Ross Thompson
824f37bba4 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-05 10:39:06 -05:00
Ross Thompson
81c44a4cb3 Fixed imperas linux testbench. 2023-10-04 17:11:47 -05:00
David Harris
28752303be Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there 2023-10-04 12:28:12 -07:00
David Harris
c6631ef808 Added N and PBMT bits to MMU PTE 2023-08-24 19:44:46 -07:00
Ross Thompson
59022099c7 Fixed the icache and dcache overlogging issue. 2023-07-14 15:47:05 -05:00
Ross Thompson
33d8e5687e Merge branch 'main' of github.com:ross144/cvw 2023-07-11 15:09:07 -05:00
Ross Thompson
99073a70c0 Added wfi and interrupt to tracer. 2023-07-11 15:09:04 -05:00
Ross Thompson
625192d9a4 Merge branch 'main' of github.com:ross144/cvw into main 2023-07-11 15:08:26 -05:00
Ross Thompson
4653f8e704 Simplificaiton of function tracker. 2023-07-11 10:51:17 -05:00
Ross Thompson
27f6f00402 Changes for xcelium. 2023-07-07 18:22:28 -05:00
David Harris
001d3cfdc5 Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
David Harris
c2913f49a3 Added assertions for ZICNTR and ZIHPM 2023-06-16 09:26:02 -07:00
Ross Thompson
4428babda9 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
d2219023c3 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
Ross Thompson
75b5c23edd Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
David Harris
45ee4c2f9f Added BMU instructions to instruction name decoder 2023-06-15 09:26:09 -07:00
Ross Thompson
301d54fea8 Significant refactoring of testbench. 2023-06-14 17:02:49 -05:00
Ross Thompson
4d2bb0ea83 Removed old configs from function name module. 2023-06-14 16:35:55 -05:00
David Harris
f68b9c224a Fixed WALLY-trap test case to use menvcfg 2023-06-09 15:24:26 -07:00
Ross Thompson
1ceea51d8b Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00