Jordan Carlin
6f79dca9c4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-27 12:29:24 -07:00
Rose Thompson
ff611016c7
Closer?
2024-05-27 14:11:02 -05:00
Rose Thompson
26c6eec832
Getting closer to functional coverage integration.
2024-05-27 13:20:18 -05:00
Rose Thompson
2985cfb7eb
Preliminary work to merge functional coverage into wally.do.
2024-05-27 11:59:13 -05:00
Rose Thompson
c9b59c8b99
Merge pull request #815 from quswarabid/covergen
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Covergen
2024-05-27 10:42:29 -05:00
Quswar Abid
997b5901cc
sb types are all passing, loaditypes are not!
2024-05-27 04:27:50 -07:00
Quswar Abid
1bf9b13953
added some sb types
2024-05-27 03:58:38 -07:00
Quswar Abid
29d7cd5663
unwanted comments
2024-05-27 03:58:38 -07:00
Quswar Abid
8edc4057ed
compilable tests generating for loaditypes[lb, lh, lw, ld, lbu, lhu, lwu]
2024-05-27 03:58:38 -07:00
David Harris
14b9223390
Merge pull request #813 from jordancarlin/fround_fixes
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Fround fixes
2024-05-26 23:54:21 +02:00
Jordan Carlin
6f7a802b86
Merge branch 'main' of https://github.com/openhwgroup/cvw into fround_fixes
2024-05-26 14:40:26 -07:00
Jordan Carlin
b830d20f2d
Modify Fround Tmask to work for X=1
2024-05-25 12:56:02 -07:00
Rose Thompson
153e66c4bb
Merge pull request #810 from davidharrishmc/dev
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Zk simplification
2024-05-25 11:52:56 -05:00
Jordan Carlin
fb77440a64
Update fpctrl fmt to work for fround instructions
2024-05-24 15:33:45 -07:00
Jordan Carlin
ae29a9b861
Update control bits for froundnx
2024-05-24 15:19:20 -07:00
David Harris
cfe83f5b49
Added derived configs to test Zb* and Zk* individually
2024-05-24 15:18:36 -07:00
Jordan Carlin
dcafe4793e
Add froundnx and fround.d tests
2024-05-24 15:16:35 -07:00
Rose Thompson
dc09e1c0c5
Modified names so they don't conflict with FPGA's axi signals.
2024-05-24 16:38:47 -05:00
Rose Thompson
73261e7f89
More cleanup. Close to the simpliest it can be.
2024-05-24 16:34:33 -05:00
Rose Thompson
bd2ec879d2
Removed unused axi signals from packetizer.
2024-05-24 16:31:27 -05:00
David Harris
a95977590d
AES cleanup
2024-05-24 14:28:30 -07:00
Rose Thompson
263be86119
Packetizer cleanup.
2024-05-24 16:27:09 -05:00
David Harris
b2689b4f01
AES cleanup
2024-05-24 14:13:57 -07:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Rose Thompson
d341974c5b
Have rvvi to ethernet working.
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Now it is time to move the hardware to the FPGA.
Ideally I don't want Wally to actually have any of this code since it's entirely
debug code so it will move to the fpga/src directory.
Then we'll need to add additional logic to the mmcm to generate the correct clocks.
Finally we'll update the I/O to add ethernet.
2024-05-24 15:52:13 -05:00
David Harris
ec5c67a5c1
AES cleanup
2024-05-24 13:48:53 -07:00
Rose Thompson
bf9f45d319
We have a simulation of the ethernet transmission working.
...
This commit does not include the source files for the ethernet as it does not belong to cvw.
I'll want to fork that repo and make it a submodule as I need to change the source a bit.
2024-05-24 11:25:42 -05:00
David Harris
e626052ec9
simplified AES32de mixcolumns because input is only one byte
2024-05-23 22:30:25 -07:00
David Harris
b0d1344121
Commented sha instructions
2024-05-23 22:06:37 -07:00
Rose Thompson
5b7b23fd64
Merge pull request #812 from jordancarlin/revert-811-dev
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Revert "Remove existing derived configs before creating new ones" and remove in derivgen.pl instead
2024-05-23 16:05:19 -05:00
Jordan Carlin
a1e22adc1e
Delete deriv directory in derivgen.pl before remaking derived configs
2024-05-23 14:01:13 -07:00
Jordan Carlin
6a2192db6e
Revert "Remove existing derived configs before creating new ones"
2024-05-23 13:56:38 -07:00
Rose Thompson
fc6814909d
Merge pull request #811 from jordancarlin/dev
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Remove existing derived configs before creating new ones
2024-05-23 15:28:59 -05:00
Jordan Carlin
fb8e97dd04
Remove existing derived configs before creating new ones
2024-05-23 13:17:24 -07:00
David Harris
ac153bc4ed
More simplifying sha512_32
2024-05-23 05:46:56 -07:00
David Harris
d9a1691c83
Simplified sha512_32
2024-05-23 05:39:50 -07:00
David Harris
c160ced2d2
Zk* cleanup
2024-05-22 15:01:20 -07:00
David Harris
3ad815ce34
Reordered Zicond support in ALU
2024-05-22 08:29:08 -07:00
Rose Thompson
e5b8fd35b0
Successfully added RVVIStall for back pressure to slow down the pipeline if the ethernet or host computer running imperasDV can't keep up.
2024-05-22 09:56:12 -05:00
David Harris
a17204b0fe
Continued bmu cleanup
2024-05-22 00:48:04 -07:00
David Harris
88eb7bd045
Pulled brev8 out of byteop so redundant byteop logic is not needed in zbkb
2024-05-22 00:22:53 -07:00
Rose Thompson
b116c0c902
Lots of progress on the rvvisynth to ethernet packetizer.
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Almost producing axi4 commands.
2024-05-21 18:23:42 -05:00
Rose Thompson
d1141237ee
Removed prefix from rvvi hierarchy so it works without testbench.
2024-05-21 16:20:53 -05:00
Rose Thompson
8fd278b322
Fixed some references to rvvi.
2024-05-21 16:15:05 -05:00
Rose Thompson
ea5d780adf
Closer to synthesized rvvi
2024-05-21 12:42:43 -05:00
David Harris
af75140bbc
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-05-21 00:50:15 -07:00
David Harris
d9ac37d771
Merge pull request #807 from ross144/main
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Improved README
2024-05-21 09:48:30 +02:00
Jordan Carlin
f410bbb79e
Use Zfa tests from riscv-arch-test instead of wally-riscv-arch-test
2024-05-21 00:04:27 -07:00
Rose Thompson
b127c19242
Merge branch 'main' into rvvi
2024-05-20 16:31:06 -05:00
Rose Thompson
d6b4a1fc83
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-20 16:23:57 -05:00
