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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
commit
c9b59c8b99
1
Makefile
1
Makefile
@ -89,6 +89,7 @@ riscvdv_functcov:
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combine_functcov:
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mkdir -p ${SIM}/questa/functcov
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mkdir -p ${SIM}/questa/functcov_logs
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cd ${SIM}/questa/functcov && rm -rf *
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run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1
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run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1
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@ -31,6 +31,12 @@ def signedImm12(imm):
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imm = imm - 0x1000
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return str(imm)
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def signedImm20(imm):
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imm = imm % pow(2, 20)
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if (imm & 0x80000):
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imm = imm - 0x100000
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return str(imm)
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def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen):
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lines = "\n# Testcase " + str(desc) + "\n"
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if (rs1val < 0):
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@ -48,6 +54,26 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, stor
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elif (test in itype):
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lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n"
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lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n"
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elif (test in loaditype):#["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]
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lines = lines + "auipc x" + str(rs1) + ", 0x20" + " # add upper immediate value to pc \n"
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lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # add immediate to lower part of rs1 \n"
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lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
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elif (test in stypes):#["sb", "sh", "sw", "sd"]
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#lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
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lines = lines + test + " x" + str(rs2) + ", " "0(x" + str(rs1) + ") # perform operation \n"
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#print("Error: %s type not implemented yet" % test)
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elif (test in btypes):#["beq", "bne", "blt", "bge", "bltu", "bgeu"]
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if (randint(1,100) > 50):
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rs1val = rs2val
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lines = lines + "# same values in both registers\n"
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lines = lines + "nop\n"
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lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value that should get changed\n"
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lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2 to a random value that should get changed\n"
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lines = lines + test + " x" + str(rs1) + ", x" + str(rs2) + ", some_label_for_sb_types_" + str(immval) + "+4" + " # perform operation \n"
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lines = lines + "addi x0, x1, 1\n"
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lines = lines + "some_label_for_sb_types_" + str(immval) + ":\n"
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lines = lines + "addi x0, x2, 2\n"
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lines = lines + "nop\nnop\nnop\nnop\nnop\n"
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else:
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pass
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#print("Error: %s type not implemented yet" % test)
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@ -130,12 +156,12 @@ def make_rd_maxvals(test, storecmd, xlen):
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def make_rd_rs1_eqval(test, storecmd, xlen):
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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desc = "cmp_rdm_rs1_eqval (Test rs1 = rd = " + hex(rs1val) + ")"
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writeCovVector(desc, rs1, 0, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
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writeCovVector(desc, rs1, 0, rd, rdval, rs2val, immval, rdval, test, storecmd, xlen)
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def make_rd_rs2_eqval(test, storecmd, xlen):
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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desc = "cmp_rd_rs2_eqval (Test rs2 = rd = " + hex(rs2val) + ")"
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writeCovVector(desc, 0, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
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writeCovVector(desc, 0, rs2, rd, rs1val, rdval, immval, rdval, test, storecmd, xlen)
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def make_rs1_rs2_eqval(test, storecmd, xlen):
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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@ -207,17 +233,37 @@ def write_tests(coverpoints, test, storecmd, xlen):
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elif (coverpoint == "cp_rs2_sign"):
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make_rs2_sign(test, storecmd, xlen)
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elif (coverpoint == "cp_rd_sign"):
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pass # hope already covered by rd_maxvals
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pass #TODO hope already covered by rd_maxvals
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elif (coverpoint == "cr_rs1_rs2"):
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make_cr_rs1_rs2_sign(test, storecmd, xlen)
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elif (coverpoint == "cp_rs1_toggle"):
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pass # toggle not needed and seems to be covered by other things
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pass #TODO toggle not needed and seems to be covered by other things
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elif (coverpoint == "cp_rs2_toggle"):
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pass # toggle not needed and seems to be covered by other things
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pass #TODO toggle not needed and seems to be covered by other things
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elif (coverpoint == "cp_rd_toggle"):
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pass # toggle not needed and seems to be covered by other things
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pass #TODO toggle not needed and seems to be covered by other things
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elif (coverpoint == "cp_gpr_hazard"):
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pass # not yet implemented
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pass #TODO not yet implemented
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elif (coverpoint == "cp_imm_sign"):
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pass #TODO
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elif (coverpoint == "cr_rs1_imm"):
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pass #TODO (not if crosses are not needed)
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elif (coverpoint == "cp_imm_ones_zeros"):
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pass #TODO
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elif (coverpoint == "cp_mem_hazard"):
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pass #TODO
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elif (coverpoint == "cp_imm_zero"):
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pass #TODO
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elif (coverpoint == "cp_mem_unaligned"):
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pass #TODO
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elif (coverpoint == "cp_offset"):
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pass #TODO
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elif (coverpoint == "cr_nord_rs1_rs2"):
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pass #TODO (not if crosses are not needed)
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elif (coverpoint == "cp_imm_shift"):
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pass #TODO
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elif (coverpoint == "cp_rd_boolean"):
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pass #TODO
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else:
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print("Warning: " + coverpoint + " not implemented yet for " + test)
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@ -238,6 +284,7 @@ def getcovergroups(coverdefdir, coverfiles):
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if (m):
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coverpoints[curinstr].append(m.group(1))
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f.close()
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print(coverpoints)
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return coverpoints
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##################################
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@ -258,6 +305,8 @@ shiftitype = ["slli", "srli", "srai"]
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itype = ["addi", "slti", "sltiu", "xori", "ori", "andi"]
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stypes = ["sb", "sh", "sw", "sd"]
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btypes = ["beq", "bne", "blt", "bge", "bltu", "bgeu"]
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# TODO: auipc missing, check whatelse is missing in ^these^ types
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coverpoints = getcovergroups(coverdefdir, coverfiles)
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author = "David_Harris@hmc.edu"
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