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105 Commits

Author SHA1 Message Date
naichewa
e3d8162279 harris code review 3 2023-11-01 10:14:15 -07:00
naichewa
2330f4ee63 hardware interlock 2023-10-30 17:00:20 -07:00
naichewa
0ff9ce527d Merge branch 'main' into spi 2023-10-16 22:59:50 -07:00
naichewa
4941fe1769 sync fifo passes 2023-10-16 22:57:02 -07:00
David Harris
fab9fbd7f1 Merged testbench 2023-10-16 13:52:24 -07:00
David Harris
ac4216b43d Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
Rose Thompson
c1d6fddea8 Removed P.FPGA from testbench. 2023-10-13 14:08:17 -05:00
naichewa
d5d4f9d044 transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
b756b248b4 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
9a49ec0b98 Removed duplicate signal name from testbench. 2023-07-07 16:34:08 -05:00
Ross Thompson
2ce8b66574 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
001d3cfdc5 Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
Ross Thompson
a8f11dcad0 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
7f79c0a855 Modified the testbench to generate the required files for embench scripts. 2023-06-16 12:27:22 -05:00
Ross Thompson
4d76e83318 embench testbench no longer crashes. 2023-06-16 11:54:41 -05:00
Ross Thompson
f3d35f914a Have the linux testbench working in the mean time. Before the consolidation. 2023-06-15 16:18:37 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
af046d4772 Major cleanup of testbench. 2023-06-15 14:57:05 -05:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Ross Thompson
301d54fea8 Significant refactoring of testbench. 2023-06-14 17:02:49 -05:00
Ross Thompson
4d2bb0ea83 Removed old configs from function name module. 2023-06-14 16:35:55 -05:00
Ross Thompson
8f09e17dc7 Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x. 2023-06-14 14:11:25 -05:00
Ross Thompson
6330e8084c more testbench improvements. 2023-06-14 12:23:26 -05:00
Ross Thompson
6e42b9f865 Continued improvements to testbench. 2023-06-14 12:11:55 -05:00
Ross Thompson
10c6c08136 Resolved the duplicated check signature issue. 2023-06-14 11:50:12 -05:00
Ross Thompson
3a78d4ca73 Fixed another issue with the timing of memory resets in the new testbench. 2023-06-13 16:24:38 -05:00
Ross Thompson
af8ca85a5b Now have most of the regression tests running again. 2023-06-13 15:09:40 -05:00
Ross Thompson
836bc4a4f7 Cleaned up testbench more. 2023-06-13 14:05:17 -05:00
Ross Thompson
4bdecf8c6d Compacted memory resets. 2023-06-13 13:57:58 -05:00
Ross Thompson
91a22c3a8a More cleanup. 2023-06-13 13:54:07 -05:00
Ross Thompson
9869b26556 Fixed the multliple reads of the same preload memory file. 2023-06-13 13:52:02 -05:00
Ross Thompson
df62f3964c The testbench now at least runs the arch64i in rv64gc config. Still has several issues 
1. need to remove all dead code
2. seems to still be double reading memory files sometimes.
3. batch mode does not work.
 2023-06-13 13:18:46 -05:00
Ross Thompson
fe72264de3 The new testbench is almost working except the shadow copy is not working. 2023-06-12 15:08:23 -05:00
Ross Thompson
9eeac21113 Progress towards new testbench. 2023-06-12 14:06:17 -05:00
Ross Thompson
ee4352975c This parameterizes the testbench but does not use the verilator updates or the new testbench. 2023-06-12 11:00:30 -05:00
Ross Thompson
8d1dee5764 Removed comments around commented code for verilator. 2023-06-11 15:30:51 -05:00
Ross Thompson
e27dfb8ce0 Merge branch 'verilator' 2023-06-11 15:28:04 -05:00
Ross Thompson
39c8f11191 Fixed the garbled output in embench transcript. 2023-06-08 10:43:46 -05:00
Ross Thompson
918464c236 Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. 2023-06-05 15:42:05 -05:00
Ross Thompson
1ceea51d8b Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00
Ross Thompson
04d0fd94f0 Merge branch 'param-lim-merge' 2023-05-26 16:25:35 -05:00
Ross Thompson
88cc473c68 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-24 13:00:50 -05:00
Ross Thompson
930fb67308 Trying to figure out why the parameterization slowed down modelsim so much. 2023-05-24 12:44:42 -05:00
Ross Thompson
2ddb8c7c78 Merge pull request #297 from davidharrishmc/dev 
Verilator testbench changes
 2023-05-22 13:29:54 -04:00
David Harris
163b05f1ce Removed force from branch predictor initialization 2023-05-22 09:57:41 -07:00
David Harris
84dac82def Initial testbench cleanup for Verilator 2023-05-22 09:51:46 -07:00
Ross Thompson
664231c0da Merge branch 'localhistory' 
Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
 2023-05-22 10:13:31 -05:00
David Harris
7b0d1a7883 Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim 2023-05-16 11:37:01 -07:00
Ross Thompson
3a98fb8680 Baseline localhistory with speculative repair built. 2023-05-05 15:23:45 -05:00