David Harris
e3bf8db80b
trap.sv comment cleanup
2021-07-17 16:01:07 -04:00
David Harris
b2c2194478
trap.sv cleanup
2021-07-17 15:57:10 -04:00
David Harris
777e983c19
Finished removing PageTableEntry redundant signals from hptw
2021-07-17 15:50:52 -04:00
David Harris
348e69c096
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:24:26 -04:00
David Harris
49ec45d04d
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:22:24 -04:00
David Harris
e55546da34
hptw: Propagating PageTableEntryF removal through IFU
2021-07-17 15:04:39 -04:00
David Harris
bf56000f4e
hptw: Propagating PageTableEntryF removal through LSU
2021-07-17 15:01:01 -04:00
David Harris
d6b8a5e595
hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE
2021-07-17 14:48:44 -04:00
David Harris
ef03ec275c
hptw: Added ValidLeaf and ValidNonLeaf for readability, renamed _WDV to _READ states
2021-07-17 14:36:27 -04:00
David Harris
d19679f213
hptw: Eliminated A and D bit faults while walking page table, per spec
2021-07-17 14:29:20 -04:00
David Harris
ad44835e6e
hptw: Simplified TranslationVAdr calculation based just on DTLBWalk
2021-07-17 14:16:33 -04:00
David Harris
af02437c3a
hptw: renamed DTLBMissQ to DTLBWalk
2021-07-17 14:13:00 -04:00
David Harris
8e966b37f2
hptw: renamed ADRE to ADR
2021-07-17 14:02:59 -04:00
David Harris
95d49e4e9b
hptw: replaced PreviousWalkerState with a PageType FSM
2021-07-17 13:54:58 -04:00
David Harris
964f0d9f53
hptw: removed ITLBMissFQ
2021-07-17 13:44:08 -04:00
David Harris
9741b01465
hptw: minor cleanup
2021-07-17 13:40:12 -04:00
David Harris
ee784c19a5
hptw: Simplifed out AnyTLBMiss
2021-07-17 12:07:51 -04:00
David Harris
40989c4e3d
hptw: Renamed Memstore to MemWrite
2021-07-17 12:01:43 -04:00
David Harris
ddd9110f7b
hptw: Merged RV32/64 FSMs
2021-07-17 11:55:24 -04:00
David Harris
36a8d23222
hptw: FSM simplification
2021-07-17 11:41:43 -04:00
David Harris
6d28f3fe08
hptw: default state should be unreachable
2021-07-17 11:33:16 -04:00
David Harris
ef83a44c4d
hptw: factored Misaligned
2021-07-17 11:31:16 -04:00
David Harris
e3b26b7b23
hptw: factored HPTWRead
2021-07-17 11:25:59 -04:00
David Harris
1bbc932bfd
hptw: factored HPTWRead
2021-07-17 11:25:52 -04:00
David Harris
37cc2ca30f
hptw: factored pregen
2021-07-17 11:11:10 -04:00
David Harris
1595e4f992
HPTW: more cleanup
2021-07-17 04:55:01 -04:00
David Harris
b74f3b14ec
HPTW: factored out DTLBWrite/ITLBWrite
2021-07-17 04:44:23 -04:00
David Harris
9775294a6f
HPTW: factored out PageTableENtry
2021-07-17 04:40:01 -04:00
David Harris
f168bd6749
more cleaning up FSM
2021-07-17 04:35:51 -04:00
David Harris
e2600bc55d
cleaning up FSM
2021-07-17 04:26:41 -04:00
David Harris
52a7dd9ac0
Simplify FSM
2021-07-17 04:12:31 -04:00
David Harris
31a3b39e5c
Pulled TranslationPAdr mux out of HPTW FSM
2021-07-17 04:06:26 -04:00
David Harris
7eb03c2ff6
Simplified bad PTE detection
2021-07-17 03:30:17 -04:00
David Harris
b8ee8a8ce0
Pulled out shared PTEReg
2021-07-17 03:21:09 -04:00
David Harris
d3974fafdd
Flip-flop clean-up
2021-07-17 03:15:47 -04:00
David Harris
de72dff382
Flip-flop clean-up
2021-07-17 03:12:24 -04:00
David Harris
a5ac606dda
Flip-flop clean-up
2021-07-17 03:10:17 -04:00
David Harris
2b0f8e9cf6
Started pagetablewalker cleanup: combined state flops shared for both RV versions
2021-07-17 02:53:52 -04:00
David Harris
fe8910437a
Replaced separate PageTypeF and PageTypeM with common PageType
2021-07-17 02:31:23 -04:00
David Harris
622a14cbdd
Removed more unused signals from ahblite
2021-07-17 02:21:54 -04:00
David Harris
52fcc47cdf
Removed rest of HRDATAW from ahblite
2021-07-17 02:15:24 -04:00
David Harris
1d171d7ea6
Commented out HRDATAW logic in ebu
2021-07-17 02:10:57 -04:00
David Harris
d6f859da18
renamed or_rows.sv
2021-07-16 20:17:03 -04:00
Ross Thompson
e9649eb1f5
Made furture progress in the mmu tests.
2021-07-16 15:56:06 -05:00
Ross Thompson
abce241f68
Also changed the shadow ram's dcache copy widths.
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Merge branch 'dcache' into main
2021-07-16 14:21:09 -05:00
Ross Thompson
d3715acf2d
Fixed walker fault interaction with dcache.
2021-07-16 12:22:13 -05:00
Ross Thompson
5ca7dc619c
Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
2021-07-16 11:12:57 -05:00
Kip Macsai-Goren
ba5bb12e26
Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
2021-07-15 18:30:29 -04:00
Ross Thompson
96aa106852
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
2021-07-15 11:56:35 -05:00
Ross Thompson
4549a9f1c9
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
c39a228266
Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
2021-07-15 11:00:42 -05:00
Ross Thompson
c954fb510b
Renamed DCacheStall to LSUStall in hart and hazard.
...
Added missing logic in lsu.
2021-07-15 10:16:16 -05:00
Ross Thompson
f234875779
dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
2021-07-14 23:08:07 -05:00
Ross Thompson
6163629204
Finally have the ptw correctly walking through the dcache to update the itlb.
...
Still not working fully.
2021-07-14 22:26:07 -05:00
Katherine Parry
701ea38964
Fixed lint warning
2021-07-14 21:24:48 -04:00
Ross Thompson
d41c9d5ad9
Added d cache StallW checks for any time the cache wants to go to STATE_READY.
2021-07-14 17:25:50 -05:00
Ross Thompson
d3a1a2c90a
Fixed d cache not honoring StallW for uncache writes and reads.
2021-07-14 17:23:28 -05:00
Katherine Parry
f8b76082e4
fpu unpacking unit created
2021-07-14 17:56:49 -04:00
Ross Thompson
771c7ff130
Routed CommittedM and PendingInterruptM through the lsu arb.
2021-07-14 16:18:09 -05:00
Ross Thompson
1d7aa27316
Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled.
2021-07-14 15:47:38 -05:00
Ross Thompson
3092e5acdf
Forgot to include one hot decoder.
2021-07-14 15:46:52 -05:00
Ross Thompson
e17de4eb11
Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
...
This solves the committedM issue.
2021-07-14 15:00:33 -05:00
James Stine
a2c0753edb
put back for now to test fdiv
2021-07-14 06:48:29 -05:00
Ross Thompson
ef598d0e79
Implemented uncached reads.
2021-07-13 23:03:09 -05:00
Ross Thompson
b6e5670bc3
Added CommitedM to data cache output.
2021-07-13 22:43:42 -05:00
Ross Thompson
278bbfbe3c
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
James E. Stine
45a6e96673
mod 2 of fpdivsqrt update
2021-07-13 16:59:17 -04:00
James E. Stine
d695be3ad0
Update fpdivsqrt item until move into uarch
2021-07-13 16:53:20 -04:00
Ross Thompson
b780e471b4
Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled.
2021-07-13 14:51:42 -05:00
Ross Thompson
51249a0e04
Fixed the fetch buffer accidental overwrite on eviction.
2021-07-13 14:21:29 -05:00
Ross Thompson
2034a6584f
Dcache AHB address generation was wrong. Needed to zero the offset.
2021-07-13 14:19:04 -05:00
Ross Thompson
ee09fa5f58
Moved StoreStall into the hazard unit instead of in the d cache.
2021-07-13 13:20:50 -05:00
David Harris
516b710db6
Fixed busybear by restoring InstrValidW needed by testbench
2021-07-13 14:17:36 -04:00
Ross Thompson
2004b2e044
Fixed back to back store issue.
...
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
2021-07-13 12:46:20 -05:00
David Harris
9af5cef65a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 13:26:51 -04:00
David Harris
283c2cda0e
added or.sv
2021-07-13 13:26:40 -04:00
Katherine Parry
b9edbb15eb
Fixed writting MStatus FS bits
2021-07-13 13:22:04 -04:00
Katherine Parry
acdd2e4504
Fixed writting MStatus FS bits
2021-07-13 13:20:30 -04:00
David Harris
68d1f87101
Fixed InstrValid from W to M stage for CSR performance counters
2021-07-13 13:19:13 -04:00
Ross Thompson
40922cf064
Fixed subword write. subword read should not feed into subword write.
2021-07-13 11:21:44 -05:00
David Harris
4be1e8617f
Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
2021-07-13 09:32:02 -04:00
Ross Thompson
9fe6190763
Team work on solving the dcache data inconsistency problem.
2021-07-12 23:46:32 -05:00
Ross Thompson
8ca8b9075d
Progress towards the test bench flush.
2021-07-12 14:22:13 -05:00
Katherine Parry
a4bd128978
fcvt.sv cleanup
2021-07-11 21:30:01 -04:00
Katherine Parry
0cc07fda1b
Almost all convert instructions pass Imperas tests
2021-07-11 18:06:33 -04:00
Ross Thompson
282bde7205
Fixed the spurious AHB requests to address 0. Somehow by not having a default
...
(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
2021-07-10 22:34:47 -05:00
Ross Thompson
d9fa3af94d
Loads are working.
...
There is a bug when the icache stalls 1 cycle before the d cache.
2021-07-10 22:15:44 -05:00
Ross Thompson
a82c4c99c2
Actually writes the correct data now on stores.
2021-07-10 17:48:47 -05:00
Ross Thompson
ee72178eec
Write miss with eviction works.
2021-07-10 15:17:40 -05:00
Ross Thompson
0a6c86af94
Write Hits and Write Misses without eviction are working correctly! The next
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step is to add eviction of dirty lines.
2021-07-10 10:56:25 -05:00
David Harris
e6fb590187
added missing tlbmixer.sv
2021-07-09 19:18:23 -04:00
Ross Thompson
94b29ec418
Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address.
...
I think this is do to the cycle latency of stores. We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
2021-07-09 17:14:54 -05:00
Ross Thompson
7e98610651
Design loads in modelsim, but trap is an X.
2021-07-09 15:37:16 -05:00
Ross Thompson
6abd23a61d
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
...
Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
David Harris
b09fd0d0a8
Simplified tlbmixer mux to and-or
2021-07-08 23:34:24 -04:00
David Harris
4d53a935b3
Fixed missing stall in InstrRet counter
2021-07-08 20:08:04 -04:00
Ross Thompson
2efb7a4f81
Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache.
2021-07-08 18:03:52 -05:00
Ross Thompson
6041aef263
completed read miss branch through dcache fsm.
...
The challenge now is to connect to ahb and lsu.
2021-07-08 17:53:08 -05:00
David Harris
230654ea76
Eliminate reserved bits from TLB RAM
2021-07-08 17:35:00 -04:00
David Harris
f806707cb0
Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram
2021-07-08 16:58:11 -04:00
