David Harris 4d53a935b3 Fixed missing stall in InstrRet counter		2021-07-08 20:08:04 -04:00
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cache	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-04 18:55:24 -04:00
ebu	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
fpu	Added F_SUPPORTED flag to disable floating point unit when not in MISA	2021-07-05 10:30:46 -04:00
generic	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
hazard	Merge branch 'main' into bigbadbranch	2021-07-02 11:52:26 -05:00
ieu	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
ifu	MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB	2021-07-06 15:29:42 -04:00
lsu	MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB	2021-07-06 15:29:42 -04:00
mmu	Fixed missing stall in InstrRet counter	2021-07-08 20:08:04 -04:00
muldiv	Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported	2021-07-04 19:33:46 -04:00
privileged	Fixed missing stall in InstrRet counter	2021-07-08 20:08:04 -04:00
uncore	Simplified PLIC with generate	2021-07-04 19:17:15 -04:00
wally	Merged several of the load/store/instruction access faults inside the mmu.	2021-07-06 13:43:53 -05:00