Ross Thompson 3092e5acdf Forgot to include one hot decoder.		2021-07-14 15:46:52 -05:00
..
cache	Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.	2021-07-14 15:00:33 -05:00
ebu	Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.	2021-07-09 15:16:38 -05:00
fpu
generic	Forgot to include one hot decoder.	2021-07-14 15:46:52 -05:00
hazard	Moved StoreStall into the hazard unit instead of in the d cache.	2021-07-13 13:20:50 -05:00
ieu	Moved StoreStall into the hazard unit instead of in the d cache.	2021-07-13 13:20:50 -05:00
ifu	Partially working changes to support uncached memory access. Not sure what CommitedM is.	2021-07-13 17:24:59 -05:00
lsu	Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.	2021-07-14 15:00:33 -05:00
mmu	Partially working changes to support uncached memory access. Not sure what CommitedM is.	2021-07-13 17:24:59 -05:00
muldiv
privileged	Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.	2021-07-14 15:00:33 -05:00
uncore
wally	Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.	2021-07-14 15:00:33 -05:00