Ross Thompson 282bde7205 Fixed the spurious AHB requests to address 0. Somehow by not having a default ... (else) in the fsm branch selection for STATE_READY in the d cache it was possible to take an invalid branch through the fsm.		2021-07-10 22:34:47 -05:00
..
cache	Fixed the spurious AHB requests to address 0. Somehow by not having a default	2021-07-10 22:34:47 -05:00
ebu	Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.	2021-07-09 15:16:38 -05:00
fpu	Added F_SUPPORTED flag to disable floating point unit when not in MISA	2021-07-05 10:30:46 -04:00
generic	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
hazard	Merge branch 'main' into bigbadbranch	2021-07-02 11:52:26 -05:00
ieu	Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.	2021-07-09 15:16:38 -05:00
ifu	completed read miss branch through dcache fsm.	2021-07-08 17:53:08 -05:00
lsu	Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address.	2021-07-09 17:14:54 -05:00
mmu	Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache.	2021-07-08 18:03:52 -05:00
muldiv	Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported	2021-07-04 19:33:46 -04:00
privileged	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-06 13:45:20 -05:00
uncore	Simplified PLIC with generate	2021-07-04 19:17:15 -04:00
wally	Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.	2021-07-09 15:16:38 -05:00