mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Changed names of fpga IP modules to match textbook. Updated boot.h to
use the correct clock speed for #DEFINE for UART in the zero stage bootloader.
This commit is contained in:
Rose Thompson
parent
b4bcd7b0b1
commit
8d40a0a092
@ -27,19 +27,15 @@ FPGA_VCU: PreProcessFiles IP_VCU
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# Generate IP Blocks
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.PHONY: IP_Arty IP_VCU
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IP_VCU: $(dst)/xlnx_proc_sys_reset.log \
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IP_VCU: $(dst)/sysrst.log \
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MEM_VCU \
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$(dst)/xlnx_axi_clock_converter.log \
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$(dst)/xlnx_ahblite_axi_bridge.log \
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$(dst)/xlnx_axi_crossbar.log \
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$(dst)/xlnx_axi_dwidth_conv_32to64.log \
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$(dst)/xlnx_axi_dwidth_conv_64to32.log \
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$(dst)/xlnx_axi_prtcl_conv.log
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IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
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$(dst)/clkconverter.log \
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$(dst)/ahbaxibridge.log
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IP_Arty: $(dst)/sysrst.log \
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MEM_Arty \
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$(dst)/xlnx_mmcm.log \
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$(dst)/xlnx_axi_clock_converter.log \
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$(dst)/xlnx_ahblite_axi_bridge.log
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$(dst)/mmcm.log \
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$(dst)/clkconverter.log \
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$(dst)/ahbaxibridge.log
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#$(dst)/xlnx_axi_crossbar.log \
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#$(dst)/xlnx_axi_dwidth_conv_32to64.log \
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#$(dst)/xlnx_axi_dwidth_conv_64to32.log \
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@ -89,10 +89,11 @@ report_clock_interaction -file re
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write_verilog -force -mode funcsim sim/syn-funcsim.v
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if {$board=="ArtyA7"} {
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source ../constraints/small-debug.xdc
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#source ../constraints/small-debug.xdc
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#source ../constraints/small-debug-rvvi.xdc
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} else {
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source ../constraints/vcu-small-debug.xdc
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#source ../constraints/vcu-small-debug.xdc
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source ../constraints/small-debug.xdc
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}
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@ -1,28 +0,0 @@
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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# vcu118 board
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#set partNumber xcvu9p-flga2104-2L-e
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#set boardName xilinx.com:vcu118:part0:2.4
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# kcu105 board
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#set partNumber xcku040-ffva1156-2-e
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#set boardName xilinx.com:kcu105:part0:1.7
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set ipName xlnx_ahblite_axi_bridge
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create_project $ipName . -force -part $partNumber
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if {$boardName!="ArtyA7"} {
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set_property board_part $boardName [current_project]
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}
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# really just these two lines which change
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create_ip -name ahblite_axi_bridge -vendor xilinx.com -library ip -module_name $ipName
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set_property -dict [list CONFIG.C_M_AXI_DATA_WIDTH {64} CONFIG.C_S_AHB_DATA_WIDTH {64} CONFIG.C_M_AXI_THREAD_ID_WIDTH {4}] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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launch_run -jobs 8 ${ipName}_synth_1
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wait_on_run ${ipName}_synth_1
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@ -1,28 +0,0 @@
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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#set partNumber xcvu9p-flga2104-2L-e
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#set boardName xilinx.com:vcu118:part0:2.4
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set ipName xlnx_axi_clock_converter
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create_project $ipName . -force -part $partNumber
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if {$boardName!="ArtyA7"} {
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set_property board_part $boardName [current_project]
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}
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create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName
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set_property -dict [list CONFIG.ACLK_ASYNC {1} \
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CONFIG.PROTOCOL {AXI4} \
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CONFIG.ADDR_WIDTH {32} \
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CONFIG.DATA_WIDTH {64} \
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CONFIG.ID_WIDTH {4} \
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CONFIG.MI_CLK.FREQ_HZ {208333333} \
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CONFIG.SI_CLK.FREQ_HZ {10000000}] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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launch_run -jobs 8 ${ipName}_synth_1
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wait_on_run ${ipName}_synth_1
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@ -1,32 +0,0 @@
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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# vcu118 board
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#set partNumber xcvu9p-flga2104-2L-e
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#set boardName xilinx.com:vcu118:part0:2.4
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# kcu105 board
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#set partNumber xcku040-ffva1156-2-e
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#set boardName xilinx.com:kcu105:part0:1.7
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set ipName xlnx_axi_crossbar
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create_project $ipName . -force -part $partNumber
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set_property board_part $boardName [current_project]
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create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
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set_property -dict [list CONFIG.NUM_SI {2} \
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CONFIG.DATA_WIDTH {64} \
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CONFIG.ID_WIDTH {4} \
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CONFIG.M01_S01_READ_CONNECTIVITY {0} \
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CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \
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CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \
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CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \
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CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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launch_run -jobs 8 ${ipName}_synth_1
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wait_on_run ${ipName}_synth_1
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@ -1,25 +0,0 @@
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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# vcu118 board
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#set partNumber xcvu9p-flga2104-2L-e
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#set boardName xilinx.com:vcu118:part0:2.4
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# kcu105 board
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#set partNumber xcku040-ffva1156-2-e
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#set boardName xilinx.com:kcu105:part0:1.7
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set ipName xlnx_axi_dwidth_conv_32to64
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create_project $ipName . -force -part $partNumber
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set_property board_part $boardName [current_project]
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create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
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set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_32to64}] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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launch_run -jobs 8 ${ipName}_synth_1
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wait_on_run ${ipName}_synth_1
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@ -1,27 +0,0 @@
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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# vcu118 board
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#set partNumber xcvu9p-flga2104-2L-e
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#set boardName xilinx.com:vcu118:part0:2.4
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# kcu105 board
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#set partNumber xcku040-ffva1156-2-e
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#set boardName xilinx.com:kcu105:part0:1.7
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set ipName xlnx_axi_dwidth_conv_64to32
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create_project $ipName . -force -part $partNumber
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set_property board_part $boardName [current_project]
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create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
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set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_64to32} \
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CONFIG.SI_DATA_WIDTH {64} \
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CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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launch_run -jobs 8 ${ipName}_synth_1
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wait_on_run ${ipName}_synth_1
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@ -1,25 +0,0 @@
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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# vcu118 board
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#set partNumber xcvu9p-flga2104-2L-e
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#set boardName xilinx.com:vcu118:part0:2.4
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# kcu105 board
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#set partNumber xcku040-ffva1156-2-e
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#set boardName xilinx.com:kcu105:part0:1.7
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set ipName xlnx_axi_dwidth_converter
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create_project $ipName . -force -part $partNumber
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set_property board_part $boardName [current_project]
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create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
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set_property -dict [list CONFIG.Component_Name {axi_dwidth_converter}] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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launch_run -jobs 8 ${ipName}_synth_1
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wait_on_run ${ipName}_synth_1
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@ -1,23 +0,0 @@
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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# vcu118 board
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#set partNumber xcvu9p-flga2104-2L-e
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#set boardName xilinx.com:vcu118:part0:2.4
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# kcu105 board
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#set partNumber xcku040-ffva1156-2-e
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#set boardName xilinx.com:kcu105:part0:1.7
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set ipName xlnx_axi_prtcl_conv
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create_project $ipName . -force -part $partNumber
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set_property board_part $boardName [current_project]
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create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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launch_run -jobs 8 ${ipName}_synth_1
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wait_on_run ${ipName}_synth_1
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@ -1,27 +0,0 @@
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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set ipName xlnx_mmcm
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create_project $ipName . -force -part $partNumber
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set_property board_part $boardName [current_project]
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create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
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set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
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CONFIG.NUM_OUT_CLKS {3} \
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CONFIG.CLKOUT2_USED {true} \
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CONFIG.CLKOUT3_USED {true} \
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CONFIG.CLKOUT4_USED {true} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
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CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
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CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
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CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \
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CONFIG.CLKIN1_JITTER_PS {10.0} \
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] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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launch_run -jobs 8 ${ipName}_synth_1
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wait_on_run ${ipName}_synth_1
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@ -1,26 +0,0 @@
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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#set partNumber xcvu9p-flga2104-2L-e
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#set boardName xilinx.com:vcu118:part0:2.4
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set ipName xlnx_proc_sys_reset
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create_project $ipName . -force -part $partNumber
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if {$boardName!="ArtyA7"} {
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set_property board_part $boardName [current_project]
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}
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# really just these two lines which change
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create_ip -name proc_sys_reset -vendor xilinx.com -library ip -module_name $ipName
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set_property -dict [list CONFIG.C_AUX_RESET_HIGH {1} \
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CONFIG.C_AUX_RST_WIDTH {1} \
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CONFIG.C_EXT_RESET_HIGH {1} \
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CONFIG.C_EXT_RST_WIDTH {1} \
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CONFIG.C_NUM_BUS_RST {1}] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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launch_run -jobs 8 ${ipName}_synth_1
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wait_on_run ${ipName}_synth_1
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@ -225,7 +225,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
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// 2. a second clock which is 200 MHz
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// Wally requires a slower clock. At this point I don't know what speed the atrix 7 will run so I'm initially targetting 25Mhz.
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// the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot.
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xlnx_mmcm xln_mmcm(.clk_out1(clk167),
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mmcm mmcm(.clk_out1(clk167),
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.clk_out2(clk200),
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.clk_out3(CPUCLK),
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.clk_out4(phy_ref_clk),
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@ -236,7 +236,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
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// reset controller XILINX IP
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xlnx_proc_sys_reset xlnx_proc_sys_reset_0
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sysrst sysrst
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(.slowest_sync_clk(CPUCLK),
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.ext_reset_in(1'b0),
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.aux_reset_in(south_reset),
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@ -262,7 +262,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
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// ahb lite to axi bridge
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xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0
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ahbaxibridge ahbaxibridge
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(.s_ahb_hclk(CPUCLK),
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.s_ahb_hresetn(peripheral_aresetn),
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.s_ahb_hsel(HSELEXT),
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@ -314,7 +314,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
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.m_axi_rready(m_axi_rready));
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// AXI Clock Converter
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xlnx_axi_clock_converter xlnx_axi_clock_converter_0
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clkconverter clkconverter
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(.s_axi_aclk(CPUCLK),
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.s_axi_aresetn(peripheral_aresetn),
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.s_axi_awid(m_axi_awid),
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@ -153,7 +153,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) {
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int ret = 0;
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// Initialize UART for messages
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init_uart(20000000, 115200);
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init_uart(SYSTEMCLOCK, 115200);
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// Print the wally banner
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print_uart(BANNER);
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