Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #926 from ross144/main

Browse Source 
Fix my name on multiple files and other minor changes
This commit is contained in:
David Harris 2024-08-22 03:23:17 -07:00 committed by GitHub
commit b4bcd7b0b1
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
42 changed files with 46 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
addins/cvw-arch-verif

@ -1 +1 @@
Subproject commit 07679a31750eb1054055afff0d42f467c5e87727
Subproject commit 9d54f3f8e902bb85db74305993d2fc03796b57bc

2
bin/extractFunctionRadix.sh
View File

@ -3,7 +3,7 @@
######################
## extractFunctionRadix.sh
##
## Written: Ross Thompson
## Written: Rose Thompson
## email: ross1728@gmail.com
## Created: March 1, 2021
## Modified: March 10, 2021

2
bin/wally-tool-chain-install.sh
View File

@ -2,7 +2,7 @@
###########################################
## Tool chain install script.
##
## Written: Ross Thompson ross1728@gmail.com
## Written: Rose Thompson ross1728@gmail.com
## Created: 18 January 2023
## Modified: 22 January 2023
## Modified: 23 March 2023

2
fpga/comport.setup
View File

@ -1,3 +1,3 @@
sudo chown ross:ross /dev/ttyUSB1
sudo chown rose:rose /dev/ttyUSB1
stty -F /dev/ttyUSB1 57600 cs8 -cstopb -parenb
cat /dev/ttyUSB1

2
fpga/src/wallypipelinedsocwrapper.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// wallypipelinedsocwrapper.sv
//
// Written: Ross Thompson ross1728@gmail.com 16 June 2023
// Written: Rose Thompson ross1728@gmail.com 16 June 2023
// Modified:
//
// Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog,

2
linux/testvector-generation/parseGDBtoTrace.py
View File

@ -1,7 +1,7 @@
#!/usr/bin/env python3
import sys, fileinput, re
# Ross Thompson
# Rose Thompson
# July 27, 2021
# Rewrite of the linux trace parser.

4
sim/Makefile
View File

@ -30,8 +30,8 @@ QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb
# vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt
vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb
QuestaFunctCoverage: ${SIM}/questa/fcov_ucdb/rv64gc_WALLY-COV-add.elf.ucdb
vcover merge -out ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_WALLY-COV-add.elf.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_WALLY*.ucdb -logfile ${SIM}/questa/fcov_logs/log
QuestaFunctCoverage: ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY-COV-add.elf.ucdb
vcover merge -out ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY-COV-add.elf.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY*.ucdb -logfile ${SIM}/questa/fcov_logs/log
vcover report -details -html ${SIM}/questa/fcov_ucdb/fcov.ucdb
vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg > ${SIM}/questa/fcov/fcov.log
vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -testdetails -cvg > ${SIM}/questa/fcov/fcov.testdetails.log

20
sim/questa/wave.do
View File

@ -204,7 +204,7 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
@ -657,22 +657,6 @@ add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM
add wave -noupdate -expand -group testbench /testbench/DCacheFlushStart
add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFault
add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFaultDelay
add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/clk
add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/rvvi
add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/valid
add wave -noupdate -group packetizer -color Gold /testbench/rvvi_synth/packetizer/CurrState
add wave -noupdate -group packetizer -radix unsigned /testbench/rvvi_synth/packetizer/WordCount
add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/RVVIStall
add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/rvviDelay
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWdata
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWlast
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWstrb
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWvalid
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWready
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_clk
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_txd
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_en
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_er
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {554 ns} 0} {{Cursor 4} {120089 ns} 0}
quietly wave cursor active 4
@ -690,4 +674,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {1033211 ns}
WaveRestoreZoom {0 ns} {755549 ns}

2
src/cache/cache.sv vendored
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// cache.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 7 July 2021
// Modified: 20 January 2023
//

2
src/cache/cachefsm.sv vendored
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// cachefsm.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 25 August 2021
// Modified: 20 January 2023
//

2
src/cache/subcachelineread.sv vendored
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// subcachelineread.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 4 February 2022
// Modified: 20 January 2023
//

2
src/ebu/ahbcacheinterface.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// ahbcacheinterface.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: August 29, 2022
// Modified: 18 January 2023
//

2
src/ebu/ahbinterface.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// ahbinterface.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: August 29, 2022
// Modified: 18 January 2023
//

2
src/ebu/buscachefsm.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// busfsm.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: December 29, 2021
// Modified: 18 January 2023
//

2
src/ebu/busfsm.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// busfsm.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: December 29, 2021
// Modified: 18 January 2023
//

2
src/ebu/controllerinput.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// controllerinput.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: August 31, 2022
// Modified: 18 January 2023
//

2
src/ebu/ebu.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// abhmulticontroller
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: August 29, 2022
// Modified: 18 January 2023
//

2
src/ebu/ebufsmarb.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// ebufsmarb.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 23 January 2023
// Modified: 23 January 2023
//

2
src/generic/arrs.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// arrs.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Modified: November 12, 2021
//
// Purpose: resets are typically asynchronous but need to be synchronized to

2
src/ifu/bpred/RASPredictor.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// RASPredictor.sv
//
// Written: Ross Thomposn ross1728@gmail.com
// Written: Rose Thomposn ross1728@gmail.com
// Created: 15 February 2021
// Modified: 25 January 2023
//

2
src/ifu/bpred/bpred.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// bpred.sv
//
// Written: Ross Thomposn ross1728@gmail.com
// Written: Rose Thomposn ross1728@gmail.com
// Created: 12 February 2021
// Modified: 19 January 2023
//

2
src/ifu/bpred/btb.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// btb.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: February 15, 2021
// Modified: 24 January 2023
//

2
src/ifu/bpred/gshare.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// gshare.sv
//
// Written: Ross Thompson
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Created: 16 March 2021
// Adapted from ssanghai@hmc.edu (Shreya Sanghai)

2
src/ifu/bpred/gsharebasic.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// gsharebasic.sv
//
// Written: Ross Thompson
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Created: 16 March 2021
// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.

2
src/ifu/bpred/icpred.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// icpred.sv
//
// Written: Ross Thomposn ross1728@gmail.com
// Written: Rose Thomposn ross1728@gmail.com
// Created: February 26, 2023
// Modified: February 26, 2023
//

2
src/ifu/bpred/localaheadbp.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// localaheadbp
//
// Written: Ross Thompson
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Created: 16 March 2021
//

2
src/ifu/bpred/localbpbasic.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// localbpbasic
//
// Written: Ross Thompson
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Created: 16 March 2021
//

2
src/ifu/bpred/localrepairbp.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// localrepairbp
//
// Written: Ross Thompson
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Created: 15 April 2023
//

2
src/ifu/bpred/satCounter2.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// satCounter2.sv
//
// Written: Ross Thomposn
// Written: Rose Thomposn
// Email: ross1728@gmail.com
// Created: February 13, 2021
// Modified:

2
src/ifu/bpred/twoBitPredictor.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// twoBitPredictor.sv
//
// Written: Ross Thomposn
// Written: Rose Thomposn
// Email: ross1728@gmail.com
// Created: February 14, 2021
// Modified:

2
src/ifu/irom.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// irom.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 30 January 2022
// Modified: 18 January 2023
//

2
src/ifu/spill.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// spill.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 28 January 2022
// Modified: 19 January 2023
//

2
src/lsu/atomic.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// atomic.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 31 January 2022
// Modified: 18 January 2023
//

2
src/lsu/dtim.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// dtim.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 30 January 2022
// Modified: 18 January 2023
//

2
testbench/common/DCacheFlushFSM.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// DCacheFlushFSM.sv
//
// Written: David Harris David_Harris@hmc.edu and Ross Thompson ross1728@gmail.com
// Written: David Harris David_Harris@hmc.edu and Rose Thompson ross1728@gmail.com
// Modified: 14 June 2023
//
// Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty

2
testbench/common/functionName.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// functionName.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
//
// Purpose: decode name of function
//

6
testbench/common/loggers.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// loggers.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Modified: 14 June 2023
//
// Purpose: Log branch instructions, log instruction fetches,
@ -246,8 +246,8 @@ module loggers import cvw::*; #(parameter cvw_t P,
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
initial begin
LogFile = "branch.log"; // will break some of Ross's research analysis scripts
CFILogFile = "cfi.log"; // will break some of Ross's research analysis scripts
LogFile = "branch.log"; // will break some of Rose's research analysis scripts
CFILogFile = "cfi.log"; // will break some of Rose's research analysis scripts
//LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
file = $fopen(LogFile, "w");
CFIfile = $fopen(CFILogFile, "w");

2
testbench/common/watchdog.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// watchdog.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Modified: 14 June 2023
//
// Purpose: Detects if the processor is stuck and halts the simulation

2
testbench/sdc/sdModel.sv
View File

@ -917,7 +917,7 @@ module sdModel
WRITE_DATA: begin
oeDat<=1;
outdly_cnt<=outdly_cnt+1;
datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Ross)
datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Rose)
if ( outdly_cnt > `DLY_TO_OUTP) begin // if (outdly_cnt > 47) NAC cycles elapsed

2
tests/custom/fpga-test-sdc/copyFlash.c
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// copyFlash.sv
//
// Written: Ross Thompson September 25, 2021
// Written: Rose Thompson September 25, 2021
// Modified:
//
// Purpose: copies flash card into memory

2
tests/custom/fpga-test-sdc/sdcDriver.c
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// SDC.sv
//
// Written: Ross Thompson September 25, 2021
// Written: Rose Thompson September 25, 2021
// Modified:
//
// Purpose: driver for sdc reader.

2
tests/custom/simple/fail.s
View File

@ -1,4 +1,4 @@
# Ross Thompson
# Rose Thompson
# March 17, 2021
# Oklahoma State University