mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge pull request #928 from ross144/main
Update FPGA constraints to restore support for VCU108 and increase speed to 50MHz
This commit is contained in:
David Harris
GitHub
commit
86aaf43306
@ -7,34 +7,34 @@
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create_generated_clock -name SPISDCClock -source [get_pins clk_out3_xlnx_mmcm] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK]
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##### clock #####
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set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}]
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set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}]
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set_property PACKAGE_PIN E3 [get_ports default_100mhz_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports default_100mhz_clk]
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##### RVVI Ethernet ####
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# taken from https://github.com/alexforencich/verilog-ethernet/blob/master/example/Arty/fpga/fpga.xdc
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set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
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set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
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set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
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set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
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set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
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set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv]
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set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er]
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set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk]
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set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}]
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set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}]
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set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}]
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set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}]
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set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en]
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set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col]
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set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs]
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set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk]
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set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
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set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
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set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
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set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
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set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
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set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
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set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv]
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set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er]
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set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk]
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set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}]
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set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}]
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set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}]
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set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}]
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set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en]
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set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col]
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set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs]
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set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk]
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set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
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create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk]
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create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk]
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set_false_path -to [get_ports {phy_ref_clk phy_reset_n}]
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set_output_delay 0 [get_ports {phy_ref_clk phy_reset_n}]
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set_output_delay 0.000 [get_ports {phy_ref_clk phy_reset_n}]
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##### GPI ####
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set_property PACKAGE_PIN A8 [get_ports {GPI[0]}]
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@ -87,16 +87,16 @@ set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [ge
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set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn]
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set_max_delay -from [get_ports resetn] 20.000
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set_false_path -from [get_ports resetn]
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set_property PACKAGE_PIN C2 [get_ports {resetn}]
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set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
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set_property PACKAGE_PIN C2 [get_ports resetn]
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set_property IOSTANDARD LVCMOS33 [get_ports resetn]
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set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset]
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set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset]
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set_max_delay -from [get_ports south_reset] 20.000
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set_false_path -from [get_ports south_reset]
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set_property PACKAGE_PIN D9 [get_ports {south_reset}]
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set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
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set_property PACKAGE_PIN D9 [get_ports south_reset]
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set_property IOSTANDARD LVCMOS33 [get_ports south_reset]
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@ -125,15 +125,27 @@ set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
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#set_property PULLUP true [get_ports {SDCCD}]
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# SDCDat[3]
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set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCS}]
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set_property PACKAGE_PIN D4 [get_ports SDCCS]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCS]
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set_property PULLTYPE PULLUP [get_ports SDCCS]
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# set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}]
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# set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}]
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# SDCDat[0]
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set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCIn}]
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set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCLK}]
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set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}]
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set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}]
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set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCWP}]
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set_property PACKAGE_PIN F4 [get_ports SDCIn]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCIn]
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set_property PULLTYPE PULLUP [get_ports SDCIn]
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set_property PACKAGE_PIN F3 [get_ports SDCCLK]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
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set_property PULLTYPE PULLUP [get_ports SDCCLK]
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set_property PACKAGE_PIN D3 [get_ports SDCCmd]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCmd]
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set_property PULLTYPE PULLUP [get_ports SDCCmd]
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set_property PACKAGE_PIN H2 [get_ports SDCCD]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCD]
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set_property PULLTYPE PULLUP [get_ports SDCCD]
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set_property PACKAGE_PIN G2 [get_ports SDCWP]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCWP]
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set_property PULLTYPE PULLUP [get_ports SDCWP]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
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@ -158,54 +170,54 @@ set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc
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# ddr3
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
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set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]]
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set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_cke[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}]
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set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
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@ -257,3 +269,28 @@ set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]]
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set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
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set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
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create_clock -period 40.000 -name VIRTUAL_clk_out3_mmcm -waveform {0.000 20.000}
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set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports {GPI[*]}]
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set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPI[*]}]
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set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCCD]
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set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCD]
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set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCIn]
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set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCIn]
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set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCWP]
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set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCWP]
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set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports UARTSin]
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set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSin]
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create_clock -period 12.000 -name VIRTUAL_clk_pll_i -waveform {0.000 6.000}
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set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
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set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPO[*]}]
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set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCLK]
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set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 0.000 [get_ports SDCCLK]
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set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCS]
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set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCS]
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set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCmd]
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set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCmd]
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set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
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set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -min -add_delay 0.000 [get_ports ddr3_reset_n]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -max -add_delay 80.000 [get_ports ddr3_reset_n]
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@ -3,21 +3,22 @@
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# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
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# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
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# create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
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create_generated_clock -name CLKDiv64_Gen -source [get_pins xlnx_ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q]
|
||||
# create_generated_clock -name CLKDiv64_Gen -source [get_pins #wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
|
||||
#create_generated_clock -name CLKDiv64_Gen -source [get_pins ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q]
|
||||
create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK]
|
||||
|
||||
##### GPI ####
|
||||
set_property PACKAGE_PIN E34 [get_ports {GPI[0]}]
|
||||
set_property PACKAGE_PIN M22 [get_ports {GPI[1]}]
|
||||
set_property PACKAGE_PIN AW27 [get_ports {GPI[2]}]
|
||||
set_property PACKAGE_PIN A10 [get_ports {GPI[3]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}]
|
||||
#set_property PACKAGE_PIN A10 [get_ports {GPI[3]}]
|
||||
#set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[2]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
|
||||
set_max_delay -from [get_ports {GPI[*]}] 10.000n
|
||||
set_max_delay -from [get_ports {GPI[*]}] 10.000
|
||||
|
||||
##### GPO ####
|
||||
set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}]
|
||||
@ -58,7 +59,7 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_port
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
|
||||
set_max_delay -from [get_ports reset] 15.000
|
||||
set_false_path -from [get_ports reset]
|
||||
set_property PACKAGE_PIN E34 [get_ports {reset}]
|
||||
set_property PACKAGE_PIN A10 [get_ports {reset}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {reset}]
|
||||
|
||||
|
||||
@ -69,15 +70,6 @@ set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
|
||||
|
||||
|
||||
##### calib #####
|
||||
set_property PACKAGE_PIN BA37 [get_ports calib]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports calib]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
|
||||
set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
|
||||
|
||||
|
||||
##### ahblite_resetn #####
|
||||
set_property PACKAGE_PIN AV36 [get_ports {ahblite_resetn}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
|
||||
@ -94,44 +86,34 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port
|
||||
|
||||
##### SD Card I/O #####
|
||||
|
||||
# set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}]
|
||||
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}]
|
||||
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}]
|
||||
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}]
|
||||
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}]
|
||||
# set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}]
|
||||
# set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}]
|
||||
# set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}]
|
||||
# set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK]
|
||||
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}]
|
||||
# set_property PACKAGE_PIN BB16 [get_ports SDCCLK]
|
||||
# set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}]
|
||||
# set_property PULLUP true [get_ports {SDCDat[3]}]
|
||||
# set_property PULLUP true [get_ports {SDCDat[2]}]
|
||||
# set_property PULLUP true [get_ports {SDCDat[1]}]
|
||||
# set_property PULLUP true [get_ports {SDCDat[0]}]
|
||||
# set_property PULLUP true [get_ports {SDCCmd}]
|
||||
set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
|
||||
set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
|
||||
set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
|
||||
set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
|
||||
set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}]
|
||||
set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}]
|
||||
set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK]
|
||||
|
||||
set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[3]}]
|
||||
set_property -dict {PACKAGE_PIN BF7 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[2]}]
|
||||
set_property -dict {PACKAGE_PIN BC13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[1]}]
|
||||
set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[0]}]
|
||||
set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}]
|
||||
set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCIn}]
|
||||
set_property -dict {PACKAGE_PIN BA10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCmd}]
|
||||
set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCD}]
|
||||
set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS18} [get_ports SDCCLK]
|
||||
|
||||
set_property PACKAGE_PIN AW12 [get_ports SDCCD]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports SDCCD]
|
||||
set_property PULLTYPE PULLUP [get_ports SDCCD]
|
||||
set_property PACKAGE_PIN BC16 [get_ports SDCWP]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports SDCWP]
|
||||
set_property PULLTYPE PULLUP [get_ports SDCWP]
|
||||
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
|
||||
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
|
||||
|
||||
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
|
||||
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
|
||||
#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
|
||||
#set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
|
||||
#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
|
||||
#set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
|
||||
#set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
|
||||
#set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
|
||||
#set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
|
||||
|
||||
|
||||
|
||||
@ -264,8 +246,8 @@ set_property PACKAGE_PIN D27 [get_ports {c0_ddr4_dm_dbi_n[7]}]
|
||||
set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
|
||||
|
||||
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
|
||||
#set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
|
||||
#set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
|
||||
|
||||
|
||||
|
||||
|
||||
@ -3,8 +3,5 @@ wally/wallypipelinedcore.sv: logic TrapM
|
||||
wally/wallypipelinedcore.sv: logic InstrValidM
|
||||
wally/wallypipelinedcore.sv: logic InstrM
|
||||
lsu/lsu.sv: logic IEUAdrM
|
||||
lsu/lsu.sv: logic PAdrM
|
||||
lsu/lsu.sv: logic ReadDataM
|
||||
lsu/lsu.sv: logic WriteDataM
|
||||
lsu/lsu.sv: logic MemRWM
|
||||
privileged/csrc.sv: logic HPMCOUNTER_REGW
|
||||
mmu/hptw.sv: logic SATP_REGW
|
||||
|
||||
10
fpga/constraints/marked_debug_rvvi.txt
Normal file
10
fpga/constraints/marked_debug_rvvi.txt
Normal file
@ -0,0 +1,10 @@
|
||||
wally/wallypipelinedcore.sv: logic PCM
|
||||
wally/wallypipelinedcore.sv: logic TrapM
|
||||
wally/wallypipelinedcore.sv: logic InstrValidM
|
||||
wally/wallypipelinedcore.sv: logic InstrM
|
||||
lsu/lsu.sv: logic IEUAdrM
|
||||
lsu/lsu.sv: logic PAdrM
|
||||
lsu/lsu.sv: logic ReadDataM
|
||||
lsu/lsu.sv: logic WriteDataM
|
||||
lsu/lsu.sv: logic MemRWM
|
||||
privileged/csrc.sv: logic HPMCOUNTER_REGW
|
||||
@ -1,6 +1,6 @@
|
||||
create_debug_core u_ila_0 ila
|
||||
|
||||
set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
|
||||
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
|
||||
@ -27,19 +27,15 @@ FPGA_VCU: PreProcessFiles IP_VCU
|
||||
|
||||
# Generate IP Blocks
|
||||
.PHONY: IP_Arty IP_VCU
|
||||
IP_VCU: $(dst)/xlnx_proc_sys_reset.log \
|
||||
IP_VCU: $(dst)/sysrst.log \
|
||||
MEM_VCU \
|
||||
$(dst)/xlnx_axi_clock_converter.log \
|
||||
$(dst)/xlnx_ahblite_axi_bridge.log \
|
||||
$(dst)/xlnx_axi_crossbar.log \
|
||||
$(dst)/xlnx_axi_dwidth_conv_32to64.log \
|
||||
$(dst)/xlnx_axi_dwidth_conv_64to32.log \
|
||||
$(dst)/xlnx_axi_prtcl_conv.log
|
||||
IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
|
||||
$(dst)/clkconverter.log \
|
||||
$(dst)/ahbaxibridge.log
|
||||
IP_Arty: $(dst)/sysrst.log \
|
||||
MEM_Arty \
|
||||
$(dst)/xlnx_mmcm.log \
|
||||
$(dst)/xlnx_axi_clock_converter.log \
|
||||
$(dst)/xlnx_ahblite_axi_bridge.log
|
||||
$(dst)/clkconverter.log \
|
||||
$(dst)/ahbaxibridge.log
|
||||
#$(dst)/xlnx_axi_crossbar.log \
|
||||
#$(dst)/xlnx_axi_dwidth_conv_32to64.log \
|
||||
#$(dst)/xlnx_axi_dwidth_conv_64to32.log \
|
||||
@ -48,9 +44,9 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
|
||||
# Generate Memory IP Blocks
|
||||
.PHONY: MEM_VCU MEM_Arty
|
||||
MEM_VCU:
|
||||
$(MAKE) $(dst)/xlnx_ddr4-$(board).log
|
||||
$(MAKE) $(dst)/ddr4-$(board).log
|
||||
MEM_Arty:
|
||||
$(MAKE) $(dst)/xlnx_ddr3-$(board).log
|
||||
$(MAKE) $(dst)/ddr3-$(board).log
|
||||
|
||||
# Copy files and make necessary modifications
|
||||
.PHONY: PreProcessFiles
|
||||
|
||||
@ -2,15 +2,7 @@
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
|
||||
# vcu118 board
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
# kcu105 board
|
||||
#set partNumber xcku040-ffva1156-2-e
|
||||
#set boardName xilinx.com:kcu105:part0:1.7
|
||||
|
||||
set ipName xlnx_ahblite_axi_bridge
|
||||
set ipName ahbaxibridge
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
if {$boardName!="ArtyA7"} {
|
||||
@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
set ipName xlnx_axi_clock_converter
|
||||
set ipName clkconverter
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
if {$boardName!="ArtyA7"} {
|
||||
@ -2,7 +2,7 @@
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
|
||||
set ipName xlnx_ddr3
|
||||
set ipName ddr3
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
set ipName xlnx_ddr4
|
||||
set ipName ddr4
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
@ -15,12 +15,12 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
|
||||
CONFIG.No_Controller {1} \
|
||||
CONFIG.Phy_Only {Complete_Memory_Controller} \
|
||||
CONFIG.C0.DDR4_PhyClockRatio {4:1} \
|
||||
CONFIG.C0.DDR4_TimePeriod {1200} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \
|
||||
CONFIG.C0.DDR4_BurstLength {8} \
|
||||
CONFIG.C0.DDR4_BurstType {Sequential} \
|
||||
CONFIG.C0.DDR4_CasLatency {13} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {10} \
|
||||
CONFIG.C0.DDR4_CasLatency {16} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Slot {Single} \
|
||||
CONFIG.C0.DDR4_MemoryVoltage {1.2V} \
|
||||
CONFIG.C0.DDR4_DataWidth {64} \
|
||||
@ -36,14 +36,11 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {4} \
|
||||
CONFIG.C0.DDR4_AxiAddressWidth {31} \
|
||||
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
|
||||
CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \
|
||||
CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \
|
||||
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
|
||||
CONFIG.Reference_Clock {Differential} \
|
||||
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {22} \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \
|
||||
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
|
||||
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
|
||||
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \
|
||||
CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \
|
||||
@ -106,7 +103,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
|
||||
CONFIG.C0.DDR4_CustomParts {no_file_loaded} \
|
||||
CONFIG.C0.DDR4_EN_PARITY {false} \
|
||||
CONFIG.C0.DDR4_Enable_LVAUX {false} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3359} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3332} \
|
||||
CONFIG.C0.DDR4_LR_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_LR_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_MemoryName {MainMemory} \
|
||||
@ -115,6 +112,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
|
||||
CONFIG.C0.DDR4_ODT_SKEW_2 {0} \
|
||||
CONFIG.C0.DDR4_ODT_SKEW_3 {0} \
|
||||
CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \
|
||||
CONFIG.C0.DDR4_OutputDriverImpedenceControl {RZQ/7} \
|
||||
CONFIG.C0.DDR4_PAR_SKEW {0} \
|
||||
CONFIG.C0.DDR4_Specify_MandD {false} \
|
||||
CONFIG.C0.DDR4_TREFI {0} \
|
||||
@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
set ipName xlnx_ddr4
|
||||
set ipName ddr4
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
@ -1,7 +1,7 @@
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
|
||||
set ipName xlnx_mmcm
|
||||
set ipName mmcm
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
|
||||
CONFIG.CLKOUT4_USED {true} \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
|
||||
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
|
||||
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
|
||||
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \
|
||||
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \
|
||||
CONFIG.CLKIN1_JITTER_PS {10.0} \
|
||||
] [get_ips $ipName]
|
||||
@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
set ipName xlnx_proc_sys_reset
|
||||
set ipName sysrst
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
if {$boardName!="ArtyA7"} {
|
||||
@ -5,6 +5,11 @@ set boardName $::env(XILINX_BOARD)
|
||||
set boardSubName [lindex [split ${boardName} :] 1]
|
||||
set board $::env(board)
|
||||
|
||||
#set partNumber xc7a100tcsg324-1
|
||||
#set boardName digilentinc.com:arty-a7-100:part0:1.1
|
||||
#set boardSubName arty-a7-100
|
||||
#set board ArtyA7
|
||||
|
||||
set ipName WallyFPGA
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
@ -23,20 +28,15 @@ if {$board=="ArtyA7"} {
|
||||
}
|
||||
|
||||
# read in ip
|
||||
read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci
|
||||
read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci
|
||||
read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci
|
||||
# Added crossbar - Jacob Pease <2023-01-12 Thu>
|
||||
#read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci
|
||||
#read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci
|
||||
#read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci
|
||||
#read_ip IP/xlnx_axi_prtcl_conv.srcs/sources_1/ip/xlnx_axi_prtcl_conv/xlnx_axi_prtcl_conv.xci
|
||||
import_ip IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci
|
||||
import_ip IP/ahbaxibridge.srcs/sources_1/ip/ahbaxibridge/ahbaxibridge.xci
|
||||
import_ip IP/clkconverter.srcs/sources_1/ip/clkconverter/clkconverter.xci
|
||||
|
||||
if {$board=="ArtyA7"} {
|
||||
read_ip IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/xlnx_ddr3.xci
|
||||
read_ip IP/xlnx_mmcm.srcs/sources_1/ip/xlnx_mmcm/xlnx_mmcm.xci
|
||||
import_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci
|
||||
import_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci
|
||||
} else {
|
||||
read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
|
||||
import_ip IP/ddr4.srcs/sources_1/ip/ddr4/ddr4.xci
|
||||
}
|
||||
|
||||
# read in all other rtl
|
||||
@ -46,13 +46,6 @@ read_verilog [glob -type f ../../addins/ahbsdc/sdc/*.v]
|
||||
|
||||
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset]
|
||||
|
||||
if {$board=="ArtyA7"} {
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
|
||||
} else {
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
|
||||
}
|
||||
|
||||
# define top level
|
||||
set_property top fpgaTop [current_fileset]
|
||||
@ -62,6 +55,14 @@ update_compile_order -fileset sources_1
|
||||
exec mkdir -p reports/
|
||||
exec rm -rf reports/*
|
||||
|
||||
if {$board=="ArtyA7"} {
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
|
||||
} else {
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
|
||||
}
|
||||
|
||||
report_compile_order -constraints > reports/compile_order.rpt
|
||||
|
||||
# this is elaboration not synthesis.
|
||||
@ -89,10 +90,11 @@ report_clock_interaction -file re
|
||||
write_verilog -force -mode funcsim sim/syn-funcsim.v
|
||||
|
||||
if {$board=="ArtyA7"} {
|
||||
source ../constraints/small-debug.xdc
|
||||
#source ../constraints/small-debug.xdc
|
||||
#source ../constraints/small-debug-rvvi.xdc
|
||||
} else {
|
||||
source ../constraints/vcu-small-debug.xdc
|
||||
#source ../constraints/vcu-small-debug.xdc
|
||||
source ../constraints/small-debug.xdc
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -1,32 +0,0 @@
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
|
||||
# vcu118 board
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
# kcu105 board
|
||||
#set partNumber xcku040-ffva1156-2-e
|
||||
#set boardName xilinx.com:kcu105:part0:1.7
|
||||
|
||||
set ipName xlnx_axi_crossbar
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
|
||||
|
||||
set_property -dict [list CONFIG.NUM_SI {2} \
|
||||
CONFIG.DATA_WIDTH {64} \
|
||||
CONFIG.ID_WIDTH {4} \
|
||||
CONFIG.M01_S01_READ_CONNECTIVITY {0} \
|
||||
CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \
|
||||
CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \
|
||||
CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \
|
||||
CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName]
|
||||
|
||||
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
launch_run -jobs 8 ${ipName}_synth_1
|
||||
wait_on_run ${ipName}_synth_1
|
||||
@ -1,25 +0,0 @@
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
|
||||
# vcu118 board
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
# kcu105 board
|
||||
#set partNumber xcku040-ffva1156-2-e
|
||||
#set boardName xilinx.com:kcu105:part0:1.7
|
||||
|
||||
set ipName xlnx_axi_dwidth_conv_32to64
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
|
||||
|
||||
set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_32to64}] [get_ips $ipName]
|
||||
|
||||
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
launch_run -jobs 8 ${ipName}_synth_1
|
||||
wait_on_run ${ipName}_synth_1
|
||||
@ -1,27 +0,0 @@
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
|
||||
# vcu118 board
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
# kcu105 board
|
||||
#set partNumber xcku040-ffva1156-2-e
|
||||
#set boardName xilinx.com:kcu105:part0:1.7
|
||||
|
||||
set ipName xlnx_axi_dwidth_conv_64to32
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
|
||||
|
||||
set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_64to32} \
|
||||
CONFIG.SI_DATA_WIDTH {64} \
|
||||
CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName]
|
||||
|
||||
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
launch_run -jobs 8 ${ipName}_synth_1
|
||||
wait_on_run ${ipName}_synth_1
|
||||
@ -1,25 +0,0 @@
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
|
||||
# vcu118 board
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
# kcu105 board
|
||||
#set partNumber xcku040-ffva1156-2-e
|
||||
#set boardName xilinx.com:kcu105:part0:1.7
|
||||
|
||||
set ipName xlnx_axi_dwidth_converter
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
|
||||
|
||||
set_property -dict [list CONFIG.Component_Name {axi_dwidth_converter}] [get_ips $ipName]
|
||||
|
||||
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
launch_run -jobs 8 ${ipName}_synth_1
|
||||
wait_on_run ${ipName}_synth_1
|
||||
@ -1,23 +0,0 @@
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
|
||||
# vcu118 board
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
# kcu105 board
|
||||
#set partNumber xcku040-ffva1156-2-e
|
||||
#set boardName xilinx.com:kcu105:part0:1.7
|
||||
|
||||
set ipName xlnx_axi_prtcl_conv
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
|
||||
|
||||
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
launch_run -jobs 8 ${ipName}_synth_1
|
||||
wait_on_run ${ipName}_synth_1
|
||||
@ -5,7 +5,7 @@ set partNumber xcvu095-ffva2104-2-e
|
||||
set boardName xilinx.com:vcu108:part0:1.2
|
||||
|
||||
|
||||
set ipName xlnx_ddr4
|
||||
set ipName ddr4
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
1018
fpga/src/fpgaTop.sv
1018
fpga/src/fpgaTop.sv
File diff suppressed because it is too large
Load Diff
@ -29,183 +29,183 @@
|
||||
import cvw::*;
|
||||
|
||||
module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
|
||||
(input default_100mhz_clk,
|
||||
(* mark_debug = "true" *) input resetn,
|
||||
input south_reset,
|
||||
(input logic default_100mhz_clk,
|
||||
input logic resetn,
|
||||
input logic south_reset,
|
||||
|
||||
// GPIO signals
|
||||
input [3:0] GPI,
|
||||
output [4:0] GPO,
|
||||
input logic [3:0] GPI,
|
||||
output logic [4:0] GPO,
|
||||
|
||||
// UART Signals
|
||||
input UARTSin,
|
||||
output UARTSout,
|
||||
input logic UARTSin,
|
||||
output logic UARTSout,
|
||||
|
||||
// SDC Signals connecting to an SPI peripheral
|
||||
input SDCIn,
|
||||
output SDCCLK,
|
||||
output SDCCmd,
|
||||
output SDCCS,
|
||||
input SDCCD,
|
||||
input SDCWP,
|
||||
input logic SDCIn,
|
||||
output logic SDCCLK,
|
||||
output logic SDCCmd,
|
||||
output logic SDCCS,
|
||||
input logic SDCCD,
|
||||
input logic SDCWP,
|
||||
/*
|
||||
* Ethernet: 100BASE-T MII
|
||||
*/
|
||||
output phy_ref_clk,
|
||||
input phy_rx_clk,
|
||||
input [3:0] phy_rxd,
|
||||
input phy_rx_dv,
|
||||
input phy_rx_er,
|
||||
input phy_tx_clk,
|
||||
output [3:0] phy_txd,
|
||||
output phy_tx_en,
|
||||
input phy_col, // nc
|
||||
input phy_crs, // nc
|
||||
output phy_reset_n,
|
||||
output logic phy_ref_clk,
|
||||
input logic phy_rx_clk,
|
||||
input logic [3:0] phy_rxd,
|
||||
input logic phy_rx_dv,
|
||||
input logic phy_rx_er,
|
||||
input logic phy_tx_clk,
|
||||
output logic [3:0] phy_txd,
|
||||
output logic phy_tx_en,
|
||||
input logic phy_col, // nc
|
||||
input logic phy_crs, // nc
|
||||
output logic phy_reset_n,
|
||||
|
||||
inout [15:0] ddr3_dq,
|
||||
inout [1:0] ddr3_dqs_n,
|
||||
inout [1:0] ddr3_dqs_p,
|
||||
output [13:0] ddr3_addr,
|
||||
output [2:0] ddr3_ba,
|
||||
output ddr3_ras_n,
|
||||
output ddr3_cas_n,
|
||||
output ddr3_we_n,
|
||||
output ddr3_reset_n,
|
||||
output [0:0] ddr3_ck_p,
|
||||
output [0:0] ddr3_ck_n,
|
||||
output [0:0] ddr3_cke,
|
||||
output [0:0] ddr3_cs_n,
|
||||
output [1:0] ddr3_dm,
|
||||
output [0:0] ddr3_odt
|
||||
inout logic [15:0] ddr3_dq,
|
||||
inout logic [1:0] ddr3_dqs_n,
|
||||
inout logic [1:0] ddr3_dqs_p,
|
||||
output logic [13:0] ddr3_addr,
|
||||
output logic [2:0] ddr3_ba,
|
||||
output logic ddr3_ras_n,
|
||||
output logic ddr3_cas_n,
|
||||
output logic ddr3_we_n,
|
||||
output logic ddr3_reset_n,
|
||||
output logic [0:0] ddr3_ck_p,
|
||||
output logic [0:0] ddr3_ck_n,
|
||||
output logic [0:0] ddr3_cke,
|
||||
output logic [0:0] ddr3_cs_n,
|
||||
output logic [1:0] ddr3_dm,
|
||||
output logic [0:0] ddr3_odt
|
||||
);
|
||||
|
||||
// MMCM Signals
|
||||
wire CPUCLK;
|
||||
wire c0_ddr4_ui_clk_sync_rst;
|
||||
wire bus_struct_reset;
|
||||
wire peripheral_reset;
|
||||
wire interconnect_aresetn;
|
||||
wire peripheral_aresetn;
|
||||
wire mb_reset;
|
||||
logic CPUCLK;
|
||||
logic c0_ddr4_ui_clk_sync_rst;
|
||||
logic bus_struct_reset;
|
||||
logic peripheral_reset;
|
||||
logic interconnect_aresetn;
|
||||
logic peripheral_aresetn;
|
||||
logic mb_reset;
|
||||
|
||||
// AHB Signals from Wally
|
||||
wire HCLKOpen;
|
||||
wire HRESETnOpen;
|
||||
wire [63:0] HRDATAEXT;
|
||||
wire HREADYEXT;
|
||||
wire HRESPEXT;
|
||||
wire HSELEXT;
|
||||
wire [55:0] HADDR;
|
||||
wire [63:0] HWDATA;
|
||||
wire [64/8-1:0] HWSTRB;
|
||||
wire HWRITE;
|
||||
wire [2:0] HSIZE;
|
||||
wire [2:0] HBURST;
|
||||
wire [1:0] HTRANS;
|
||||
wire HREADY;
|
||||
wire [3:0] HPROT;
|
||||
wire HMASTLOCK;
|
||||
logic HCLKOpen;
|
||||
logic HRESETnOpen;
|
||||
logic [63:0] HRDATAEXT;
|
||||
logic HREADYEXT;
|
||||
logic HRESPEXT;
|
||||
logic HSELEXT;
|
||||
logic [55:0] HADDR;
|
||||
logic [63:0] HWDATA;
|
||||
logic [64/8-1:0] HWSTRB;
|
||||
logic HWRITE;
|
||||
logic [2:0] HSIZE;
|
||||
logic [2:0] HBURST;
|
||||
logic [1:0] HTRANS;
|
||||
logic HREADY;
|
||||
logic [3:0] HPROT;
|
||||
logic HMASTLOCK;
|
||||
|
||||
// GPIO Signals
|
||||
wire [31:0] GPIOIN, GPIOOUT, GPIOEN;
|
||||
logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
|
||||
|
||||
// AHB to AXI Bridge Signals
|
||||
wire [3:0] m_axi_awid;
|
||||
wire [7:0] m_axi_awlen;
|
||||
wire [2:0] m_axi_awsize;
|
||||
wire [1:0] m_axi_awburst;
|
||||
wire [3:0] m_axi_awcache;
|
||||
wire [31:0] m_axi_awaddr;
|
||||
wire [2:0] m_axi_awprot;
|
||||
wire m_axi_awvalid;
|
||||
wire m_axi_awready;
|
||||
wire m_axi_awlock;
|
||||
wire [63:0] m_axi_wdata;
|
||||
wire [7:0] m_axi_wstrb;
|
||||
wire m_axi_wlast;
|
||||
wire m_axi_wvalid;
|
||||
wire m_axi_wready;
|
||||
wire [3:0] m_axi_bid;
|
||||
wire [1:0] m_axi_bresp;
|
||||
wire m_axi_bvalid;
|
||||
wire m_axi_bready;
|
||||
wire [3:0] m_axi_arid;
|
||||
wire [7:0] m_axi_arlen;
|
||||
wire [2:0] m_axi_arsize;
|
||||
wire [1:0] m_axi_arburst;
|
||||
wire [2:0] m_axi_arprot;
|
||||
wire [3:0] m_axi_arcache;
|
||||
wire m_axi_arvalid;
|
||||
wire [31:0] m_axi_araddr;
|
||||
wire m_axi_arlock;
|
||||
wire m_axi_arready;
|
||||
wire [3:0] m_axi_rid;
|
||||
wire [63:0] m_axi_rdata;
|
||||
wire [1:0] m_axi_rresp;
|
||||
wire m_axi_rvalid;
|
||||
wire m_axi_rlast;
|
||||
wire m_axi_rready;
|
||||
logic [3:0] m_axi_awid;
|
||||
logic [7:0] m_axi_awlen;
|
||||
logic [2:0] m_axi_awsize;
|
||||
logic [1:0] m_axi_awburst;
|
||||
logic [3:0] m_axi_awcache;
|
||||
logic [31:0] m_axi_awaddr;
|
||||
logic [2:0] m_axi_awprot;
|
||||
logic m_axi_awvalid;
|
||||
logic m_axi_awready;
|
||||
logic m_axi_awlock;
|
||||
logic [63:0] m_axi_wdata;
|
||||
logic [7:0] m_axi_wstrb;
|
||||
logic m_axi_wlast;
|
||||
logic m_axi_wvalid;
|
||||
logic m_axi_wready;
|
||||
logic [3:0] m_axi_bid;
|
||||
logic [1:0] m_axi_bresp;
|
||||
logic m_axi_bvalid;
|
||||
logic m_axi_bready;
|
||||
logic [3:0] m_axi_arid;
|
||||
logic [7:0] m_axi_arlen;
|
||||
logic [2:0] m_axi_arsize;
|
||||
logic [1:0] m_axi_arburst;
|
||||
logic [2:0] m_axi_arprot;
|
||||
logic [3:0] m_axi_arcache;
|
||||
logic m_axi_arvalid;
|
||||
logic [31:0] m_axi_araddr;
|
||||
logic m_axi_arlock;
|
||||
logic m_axi_arready;
|
||||
logic [3:0] m_axi_rid;
|
||||
logic [63:0] m_axi_rdata;
|
||||
logic [1:0] m_axi_rresp;
|
||||
logic m_axi_rvalid;
|
||||
logic m_axi_rlast;
|
||||
logic m_axi_rready;
|
||||
|
||||
// AXI Signals going out of Clock Converter
|
||||
wire [3:0] BUS_axi_arregion;
|
||||
wire [3:0] BUS_axi_arqos;
|
||||
wire [3:0] BUS_axi_awregion;
|
||||
wire [3:0] BUS_axi_awqos;
|
||||
wire [3:0] BUS_axi_awid;
|
||||
wire [7:0] BUS_axi_awlen;
|
||||
wire [2:0] BUS_axi_awsize;
|
||||
wire [1:0] BUS_axi_awburst;
|
||||
wire [3:0] BUS_axi_awcache;
|
||||
wire [31:0] BUS_axi_awaddr;
|
||||
wire [2:0] BUS_axi_awprot;
|
||||
wire BUS_axi_awvalid;
|
||||
wire BUS_axi_awready;
|
||||
wire BUS_axi_awlock;
|
||||
wire [63:0] BUS_axi_wdata;
|
||||
wire [7:0] BUS_axi_wstrb;
|
||||
wire BUS_axi_wlast;
|
||||
wire BUS_axi_wvalid;
|
||||
wire BUS_axi_wready;
|
||||
wire [3:0] BUS_axi_bid;
|
||||
wire [1:0] BUS_axi_bresp;
|
||||
wire BUS_axi_bvalid;
|
||||
wire BUS_axi_bready;
|
||||
wire [3:0] BUS_axi_arid;
|
||||
wire [7:0] BUS_axi_arlen;
|
||||
wire [2:0] BUS_axi_arsize;
|
||||
wire [1:0] BUS_axi_arburst;
|
||||
wire [2:0] BUS_axi_arprot;
|
||||
wire [3:0] BUS_axi_arcache;
|
||||
wire BUS_axi_arvalid;
|
||||
wire [31:0] BUS_axi_araddr;
|
||||
wire BUS_axi_arlock;
|
||||
wire BUS_axi_arready;
|
||||
wire [3:0] BUS_axi_rid;
|
||||
wire [63:0] BUS_axi_rdata;
|
||||
wire [1:0] BUS_axi_rresp;
|
||||
wire BUS_axi_rvalid;
|
||||
wire BUS_axi_rlast;
|
||||
wire BUS_axi_rready;
|
||||
logic [3:0] BUS_axi_arregion;
|
||||
logic [3:0] BUS_axi_arqos;
|
||||
logic [3:0] BUS_axi_awregion;
|
||||
logic [3:0] BUS_axi_awqos;
|
||||
logic [3:0] BUS_axi_awid;
|
||||
logic [7:0] BUS_axi_awlen;
|
||||
logic [2:0] BUS_axi_awsize;
|
||||
logic [1:0] BUS_axi_awburst;
|
||||
logic [3:0] BUS_axi_awcache;
|
||||
logic [31:0] BUS_axi_awaddr;
|
||||
logic [2:0] BUS_axi_awprot;
|
||||
logic BUS_axi_awvalid;
|
||||
logic BUS_axi_awready;
|
||||
logic BUS_axi_awlock;
|
||||
logic [63:0] BUS_axi_wdata;
|
||||
logic [7:0] BUS_axi_wstrb;
|
||||
logic BUS_axi_wlast;
|
||||
logic BUS_axi_wvalid;
|
||||
logic BUS_axi_wready;
|
||||
logic [3:0] BUS_axi_bid;
|
||||
logic [1:0] BUS_axi_bresp;
|
||||
logic BUS_axi_bvalid;
|
||||
logic BUS_axi_bready;
|
||||
logic [3:0] BUS_axi_arid;
|
||||
logic [7:0] BUS_axi_arlen;
|
||||
logic [2:0] BUS_axi_arsize;
|
||||
logic [1:0] BUS_axi_arburst;
|
||||
logic [2:0] BUS_axi_arprot;
|
||||
logic [3:0] BUS_axi_arcache;
|
||||
logic BUS_axi_arvalid;
|
||||
logic [31:0] BUS_axi_araddr;
|
||||
logic BUS_axi_arlock;
|
||||
logic BUS_axi_arready;
|
||||
logic [3:0] BUS_axi_rid;
|
||||
logic [63:0] BUS_axi_rdata;
|
||||
logic [1:0] BUS_axi_rresp;
|
||||
logic BUS_axi_rvalid;
|
||||
logic BUS_axi_rlast;
|
||||
logic BUS_axi_rready;
|
||||
|
||||
wire BUSCLK;
|
||||
wire sdio_reset_open;
|
||||
logic BUSCLK;
|
||||
logic sdio_reset_open;
|
||||
|
||||
wire c0_init_calib_complete;
|
||||
wire dbg_clk;
|
||||
wire [511 : 0] dbg_bus;
|
||||
wire ui_clk_sync_rst;
|
||||
logic c0_init_calib_complete;
|
||||
logic dbg_clk;
|
||||
logic [511 : 0] dbg_bus;
|
||||
logic ui_clk_sync_rst;
|
||||
|
||||
wire CLK208;
|
||||
wire clk167;
|
||||
wire clk200;
|
||||
logic CLK208;
|
||||
logic clk167;
|
||||
logic clk200;
|
||||
|
||||
wire app_sr_active;
|
||||
wire app_ref_ack;
|
||||
wire app_zq_ack;
|
||||
wire mmcm_locked;
|
||||
wire [11:0] device_temp;
|
||||
wire mmcm1_locked;
|
||||
logic app_sr_active;
|
||||
logic app_ref_ack;
|
||||
logic app_zq_ack;
|
||||
logic mmcm_locked;
|
||||
logic [11:0] device_temp;
|
||||
logic mmcm1_locked;
|
||||
|
||||
(* mark_debug = "true" *) logic RVVIStall;
|
||||
|
||||
@ -225,7 +225,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
|
||||
// 2. a second clock which is 200 MHz
|
||||
// Wally requires a slower clock. At this point I don't know what speed the atrix 7 will run so I'm initially targetting 25Mhz.
|
||||
// the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot.
|
||||
xlnx_mmcm xln_mmcm(.clk_out1(clk167),
|
||||
mmcm mmcm(.clk_out1(clk167),
|
||||
.clk_out2(clk200),
|
||||
.clk_out3(CPUCLK),
|
||||
.clk_out4(phy_ref_clk),
|
||||
@ -236,7 +236,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
|
||||
|
||||
|
||||
// reset controller XILINX IP
|
||||
xlnx_proc_sys_reset xlnx_proc_sys_reset_0
|
||||
sysrst sysrst
|
||||
(.slowest_sync_clk(CPUCLK),
|
||||
.ext_reset_in(1'b0),
|
||||
.aux_reset_in(south_reset),
|
||||
@ -262,7 +262,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
|
||||
|
||||
|
||||
// ahb lite to axi bridge
|
||||
xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0
|
||||
ahbaxibridge ahbaxibridge
|
||||
(.s_ahb_hclk(CPUCLK),
|
||||
.s_ahb_hresetn(peripheral_aresetn),
|
||||
.s_ahb_hsel(HSELEXT),
|
||||
@ -314,7 +314,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
|
||||
.m_axi_rready(m_axi_rready));
|
||||
|
||||
// AXI Clock Converter
|
||||
xlnx_axi_clock_converter xlnx_axi_clock_converter_0
|
||||
clkconverter clkconverter
|
||||
(.s_axi_aclk(CPUCLK),
|
||||
.s_axi_aresetn(peripheral_aresetn),
|
||||
.s_axi_awid(m_axi_awid),
|
||||
@ -400,7 +400,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
|
||||
.m_axi_rready(BUS_axi_rready));
|
||||
|
||||
// DDR3 Controller
|
||||
xlnx_ddr3 xlnx_ddr3_c0
|
||||
ddr3 ddr3
|
||||
(
|
||||
// ddr3 I/O
|
||||
.ddr3_dq(ddr3_dq),
|
||||
|
||||
@ -153,7 +153,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) {
|
||||
int ret = 0;
|
||||
|
||||
// Initialize UART for messages
|
||||
init_uart(20000000, 115200);
|
||||
init_uart(SYSTEMCLOCK, 115200);
|
||||
|
||||
// Print the wally banner
|
||||
print_uart(BANNER);
|
||||
|
||||
@ -21,8 +21,8 @@
|
||||
cpus {
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
clock-frequency = <0x1312D00>;
|
||||
timebase-frequency = <0x1312D00>;
|
||||
clock-frequency = <0x17D7840>;
|
||||
timebase-frequency = <0x17D7840>;
|
||||
|
||||
cpu@0 {
|
||||
phandle = <0x01>;
|
||||
@ -54,7 +54,7 @@
|
||||
refclk: refclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0x1312D00>;
|
||||
clock-frequency = <0x17D7840>;
|
||||
clock-output-names = "xtal";
|
||||
};
|
||||
|
||||
@ -73,7 +73,7 @@
|
||||
uart@10000000 {
|
||||
interrupts = <0x0a>;
|
||||
interrupt-parent = <0x03>;
|
||||
clock-frequency = <0x1312D00>;
|
||||
clock-frequency = <0x17D7840>;
|
||||
reg = <0x00 0x10000000 0x00 0x100>;
|
||||
compatible = "ns16550a";
|
||||
};
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
chosen {
|
||||
linux,initrd-end = <0x85c43a00>;
|
||||
linux,initrd-start = <0x84200000>;
|
||||
bootargs = "console=ttyS0,115200 root=/dev/vda ro";
|
||||
bootargs = "root=/dev/vda ro console=ttyS0,115200 loglevel=7";
|
||||
stdout-path = "/soc/uart@10000000";
|
||||
};
|
||||
|
||||
@ -21,8 +21,8 @@
|
||||
cpus {
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
clock-frequency = <0x14FB180>;
|
||||
timebase-frequency = <0x14FB180>;
|
||||
clock-frequency = <0x2FAF080>;
|
||||
timebase-frequency = <0x2FAF080>;
|
||||
|
||||
cpu@0 {
|
||||
phandle = <0x01>;
|
||||
@ -31,6 +31,9 @@
|
||||
status = "okay";
|
||||
compatible = "riscv";
|
||||
riscv,isa = "rv64imafdcsu";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
|
||||
riscv,cbom-block-size = <64>;
|
||||
mmu-type = "riscv,sv48";
|
||||
|
||||
interrupt-controller {
|
||||
@ -48,10 +51,29 @@
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
refclk: refclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0x2FAF080>;
|
||||
clock-output-names = "xtal";
|
||||
};
|
||||
|
||||
gpio0: gpio@10060000 {
|
||||
compatible = "sifive,gpio0";
|
||||
interrupt-parent = <0x03>;
|
||||
interrupts = <3>;
|
||||
reg = <0x00 0x10060000 0x00 0x1000>;
|
||||
reg-names = "control";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
uart@10000000 {
|
||||
interrupts = <0x0a>;
|
||||
interrupt-parent = <0x03>;
|
||||
clock-frequency = <0x14FB180>;
|
||||
clock-frequency = <0x2FAF080>;
|
||||
reg = <0x00 0x10000000 0x00 0x100>;
|
||||
compatible = "ns16550a";
|
||||
};
|
||||
@ -67,18 +89,24 @@
|
||||
#address-cells = <0x00>;
|
||||
};
|
||||
|
||||
mmc@13000 {
|
||||
interrupts = <0x14>;
|
||||
compatible = "riscv,axi-sd-card-1.0";
|
||||
reg = <0x00 0x13000 0x00 0x7F>;
|
||||
fifo-depth = <256>;
|
||||
bus-width = <4>;
|
||||
spi@13000 {
|
||||
compatible = "sifive,spi0";
|
||||
interrupt-parent = <0x03>;
|
||||
clock = <0x14FB180>;
|
||||
max-frequency = <0xA7D8C0>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
no-sdio;
|
||||
interrupts = <0x14>;
|
||||
reg = <0x0 0x13000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <&refclk>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mmc@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <5000000>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
disable-wp;
|
||||
// gpios = <&gpio0 6 1>;
|
||||
};
|
||||
};
|
||||
|
||||
clint@2000000 {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user