621 Commits

Author	SHA1	Message	Date
Rose Thompson	3cf6a19729	Merge branch 'main' into main	2024-03-10 10:48:21 -05:00
Rose Thompson	402d71e5f4	Added basic Quad testing.	2024-03-07 15:19:53 -06:00
Rose Thompson	a85ace87c7	Sold progress towards a decent q test.	2024-03-07 15:01:48 -06:00
Rose Thompson	1872966b0b	Progress.	2024-03-07 13:02:24 -06:00
Rose Thompson	24dffa39d5	Yay. David and I got our first Quad load/store instructions working!	2024-03-07 12:48:52 -06:00
Rose Thompson	60f96112db	Moved the zero stage boot loader to the fpga directory.	2024-03-01 10:23:55 -06:00
KelvinTr	01c45ab9d7	Fixed K extension changes	2024-02-28 17:05:08 -06:00
James E. Stine	0d4d996655	add spike riscof items for K extension test	2024-02-24 22:43:33 -06:00
David Harris	824bc0dab7	Fixed expected value on WALLY-satp-invalid	2024-02-16 11:12:57 -08:00
Rose Thompson	6110799a1e	Updated the wally rv32 priv tests to not use sail.	2024-02-16 11:39:06 -06:00
David Harris	b362320dd9	Removed unused Makefiles and Makefrags from wally-riscv-arch-test now that it is only used by riscof	2024-02-16 06:46:49 -08:00
David Harris	d094201362	Added NO_SAIL to wally-riscv-arch-test cases that stopped passing in Sail	2024-02-16 06:27:49 -08:00
David Harris	9ba35991e3	Finished FPU coverage	2024-02-15 20:01:28 -08:00
harshinisrinath	86c35bad9f	Wrote illegal instructions for remaining floating point instructions	2024-02-07 17:13:49 -08:00
harshinisrinath	96c8526754	Wrote illegal instructions for remaining floating point instructions	2024-02-07 17:08:19 -08:00
David Harris	e7364290e3	Restored instead of in testbench because prevents coverage analysis. Improved FPU coverage	2024-02-07 06:27:53 -08:00
David Harris	dfee790ad7	Fixed derivative generation when derivs don't already exist. Fixed lint to print success when no failures. Added Zfh fma tests. Some fp tests not running yet.	2024-02-06 12:35:56 -08:00
David Harris	5d8d82414b	Coverage improvements	2024-02-04 11:40:38 -08:00
Jordan Carlin	2dce774d34	tlb ramline coverage improvements	2024-02-03 09:50:15 -08:00
Jordan Carlin	0312476fb3	Update tlb camline ASID coverage to use single file	2024-02-03 09:48:57 -08:00
Jordan Carlin	8633f263a2	Complete coverage of tlb camlines in IFU	2024-02-01 20:41:05 -08:00
Rose Thompson	87d91c5b14	Coverage updates.	2024-02-01 12:12:01 -06:00
Rose Thompson	ccf61853cf	New coverage for ebu.	2024-01-31 14:55:25 -06:00
Rose Thompson	07d1a4104a	Improvement to ebu coverage. ... Also modified object dumps to include data segments.	2024-01-31 14:03:27 -06:00
David Harris	d9003da8e0	Moved some tests to wally-riscv-arch-test list that are simulated	2024-01-30 10:28:51 -08:00
David Harris	45e2317636	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
David Harris	3620a10c0b	Improved hptw and I CacheWays coverage	2024-01-26 14:55:51 -08:00
David Harris	1c1d3eb956	HPTW coverage improvements	2024-01-26 10:46:38 -08:00
David Harris	2449e06e55	Fixed FPU coverage, solved Issue 596 by misaligned AMO throwing access fault when misaligned non-amo are supported	2024-01-25 21:03:41 -08:00
David Harris	0e1c53f9f6	Fixed tlbmisc testing with PBMTE = 0	2024-01-24 12:24:33 -08:00
David Harris	66a1edb261	More coverage touchup	2024-01-23 23:11:49 -08:00
David Harris	7215f48dda	coverage improvements: fixing problems running ImperasDV on coverage tests	2024-01-23 22:21:01 -08:00
David Harris	d5f497eec5	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-01-22 09:56:50 -08:00
Jordan Carlin	0c13e14bbf	coverage improvements for mret when mpp = 3; update imperas config	2024-01-22 09:52:58 -08:00
David Harris	4ffa5e7b0a	Coverage improvements	2024-01-22 09:49:24 -08:00
Jordan Carlin	4936496bb9	fix sfence.inval.ir and sret coverage from previous PR	2024-01-22 08:58:31 -08:00
David Harris	171430a695	FPU and PMP tests	2024-01-21 14:41:22 -08:00
David Harris	ff055c404c	fpu coverage improvements	2024-01-21 13:17:56 -08:00
David Harris	69218b4b86	Coverage improvements	2024-01-21 10:03:07 -08:00
David Harris	9260d3c424	Add Zfh support to imperas.ic, use Zicond in riscof now that it is fixed in riscv-arch-test	2024-01-18 22:46:07 -08:00
David Harris	13de147c7e	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-01-18 22:12:07 -08:00
David Harris	17c9be7695	Cleanup typos, remove Zicond from riscof until it is working	2024-01-18 21:36:52 -08:00
Jordan Carlin	82d9467eea	Add coverage of FIOM in different privelege modes	2024-01-18 19:29:16 -08:00
Jordan Carlin	12b2baff82	add coverage of sfence.inval.ir instruction and fix sret coverage	2024-01-18 17:33:59 -08:00
naichewa	8b60992e72	fixed SPI tests failing when no icache	2024-01-17 14:38:11 -08:00
David Harris	f8c88a398a	Coverage improvements	2024-01-15 07:16:41 -08:00
Jordan Carlin	51f670c821	Merge branch 'openhwgroup:main' into main	2024-01-12 19:43:01 -08:00
Jordan Carlin	6c797570fa	Add coverage for all Zcb instructions	2024-01-12 19:10:13 -08:00
Rose Thompson	0b2af0c99a	Modifed the sv39 tests so they work with just 128MiB physical memory.	2024-01-12 20:00:21 -06:00
Rose Thompson	e6a2595936	Modified sv48 svadu test to work with 128MB rather than 2GB physical memory.	2024-01-12 11:05:06 -06:00