Rose Thompson
f1d9e18dee
Modified fpga config to support two fpga boards with different amount of memory.
...
Modified vcu108 constraints to better constrain the spi clock and in/out.
2024-08-29 16:12:58 -07:00
Rose Thompson
ee1e09a6a2
VCU108 now boot linux at 50MHz!
2024-08-23 17:18:47 -07:00
Rose Thompson
14083bc642
VCU108 is not synthesizing at 50MHz. Still running into a few problems
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with the new SPI sd card device.
2024-08-23 16:17:15 -07:00
Rose Thompson
842aea157c
Updated vc108 constraints for spi based sd card and setting 50 Mhz.
2024-08-23 15:59:11 -07:00
Rose Thompson
b471913d9f
On the way to making vcu108 work again.
2024-08-23 14:45:22 -07:00
Rose Thompson
4d56b3ca96
Maybe improvements to fpga synthesis.
2024-08-23 13:00:22 -07:00
Rose Thompson
fc80bf1251
More updates to fpga IP module names.
2024-08-22 14:31:39 -07:00
Rose Thompson
8d40a0a092
Changed names of fpga IP modules to match textbook. Updated boot.h to
...
use the correct clock speed for #DEFINE for UART in the zero stage
bootloader.
2024-08-22 13:56:50 -07:00
Rose Thompson
f603d21826
Updated my name in multiple locations.
2024-08-21 10:50:39 -07:00
Jordan Carlin
08506b5872
Remove boot.mem
2024-08-08 20:27:51 -07:00
Jacob Pease
660da55451
Turned off RVVI by default.
2024-08-08 13:50:11 -05:00
Jacob Pease
11ca2567b8
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jacob Pease
8b85a5c34a
SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree.
2024-08-06 16:57:57 -05:00
Jacob Pease
51f061ba35
Removed HSELEXTSDC and fixed SD card pin definitions.
2024-08-02 15:35:18 -05:00
Rose Thompson
13db14db6b
Factored out the rvvi testbench code into rvvitbwrapper.
2024-07-24 13:10:57 -05:00
Rose Thompson
c11036358a
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Jacob Pease
c18b3d814d
Fixed verilog bugs.
2024-07-23 17:26:39 -05:00
Jacob Pease
a722c3c0a1
Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
2024-07-22 12:36:39 -05:00
Rose Thompson
02f108345a
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
24609f0b7f
Now have configurations to switch between supporting RVVI over ethernet.
2024-07-22 10:51:13 -05:00
Rose Thompson
00840e4893
Made the fpga top level configurable between rvvi synth and not.
2024-07-19 17:35:30 -05:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Ross Thompson
6734685333
Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit.
2024-07-09 19:04:18 -05:00
Ross Thompson
ccf4bb8ddc
Maybe have the incircuit trigger working.
2024-06-26 16:15:46 -07:00
Ross Thompson
612a281f62
Added module to receive ethernet frame and trigger the ila.
2024-06-26 11:05:31 -07:00
Ross Thompson
1c6ebb86a3
Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
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Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
Ross Thompson
ab1ee3d69b
Removed *** from IFU, lrcs.
2024-06-19 09:40:35 -07:00
Ross Thompson
c5dac4d775
Removed *** from fpga top.
2024-06-19 09:28:21 -07:00
Ross Thompson
47523c97ac
Getting closer to figuring out the lost ethernet frame bugs.
2024-06-13 15:46:54 -07:00
Ross Thompson
c9f51df34a
Fixed bug in rvvi reset.
2024-06-12 14:47:32 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
Rose Thompson
6a4c8667df
Added new signals to ILA to debug the RVVI tracer.
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The tracer appears to be stuck and the CPU is never getting out of (into reset).
2024-05-30 16:43:25 -05:00
Jacob Pease
3f7659c8ad
Removed old fpgaTop.v file.
2024-05-30 16:15:19 -05:00
Jacob Pease
7ecd1c7d5f
The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
2024-05-30 15:48:27 -05:00
Rose Thompson
9703055758
The FPGA is synthesizing with the rvvi and ethernet hardware.
2024-05-30 15:37:17 -05:00
Rose Thompson
7693c5d4e2
Updates to fpga top level.
2023-12-15 15:32:05 -06:00
Rose Thompson
26cd22c388
Replaced fpga's verilog top with system verilog.
2023-12-15 13:42:52 -06:00
Rose Thompson
dab9d7ab3c
Replaced fpga top level verilog with system verilog.
2023-12-15 13:07:08 -06:00
Jacob Pease
87e6a5ccf2
Updated ROM to preload bootloader from file and infer a block ram when building for FPGA.
2023-11-18 19:15:39 -06:00
Ross Thompson
d33c966a42
Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock.
2023-10-10 17:46:12 -05:00
Jacob Pease
2bf6207919
Added help option to the flash-sd script.
2023-08-22 13:37:33 -05:00
Jacob Pease
b626f2185a
Fixed GPIO pin names in fpgaTop.v
2023-07-25 20:57:04 -05:00
Ross Thompson
b1f7a5768f
Removed all old references to the old flash card controller.
...
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
63afd95ad3
Fixed bugs in boot and new flash card merge. Works with arty a7 now.
2023-07-22 15:52:25 -05:00
Ross Thompson
ab6ef5bb58
At least it simulates and gets through fpga elaboration.
2023-07-21 18:40:26 -05:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
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Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Jacob Pease
380d96b359
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
2752e5de4c
Fixed a bunch of timing constraints for the arty a7 board.
2023-07-19 17:08:16 -05:00
Ross Thompson
97a16f75dc
Fixed typo in fpga top for arty a7.
2023-07-19 11:37:29 -05:00
Ross Thompson
e4d6a9f8c6
Removed all old configuration files.
2023-07-19 10:28:54 -05:00
