Ross Thompson 6734685333 Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit.		2024-07-09 19:04:18 -05:00
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axi_sdc_controller.v	Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock.	2023-10-10 17:46:12 -05:00
boot.mem	Updated ROM to preload bootloader from file and infer a block ram when building for FPGA.	2023-11-18 19:15:39 -06:00
fpgaTop.sv	The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.	2024-05-30 15:48:27 -05:00
fpgaTopArtyA7.sv	Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit.	2024-07-09 19:04:18 -05:00
wallypipelinedsocwrapper.sv	Merge branch 'boot' into mergeBoot	2023-07-21 17:43:45 -05:00