David Harris
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718630c378
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Reduced complexity of pmpadrdec
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2021-06-23 03:03:52 -04:00 |
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bbracker
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56b0d4d016
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added slack notifier for long sims
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2021-06-22 08:31:41 -04:00 |
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bbracker
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1f2a967e0f
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read from MSTATUS workaround because QEMU has incorrect MSTATUS
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2021-06-20 10:11:39 -04:00 |
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bbracker
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6e9c6e3e6a
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whoops wavedo typo
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2021-06-20 05:36:54 -04:00 |
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bbracker
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9469367da3
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make buildroot ignore SSTATUS because QEMU did not originally log it
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2021-06-20 05:31:24 -04:00 |
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bbracker
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52fb630379
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remove lingering busybear stuff from buildroot do files
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2021-06-20 00:50:53 -04:00 |
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bbracker
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3e32ba3684
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make buildroot waves only turn on after a user-specified point
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2021-06-20 00:39:30 -04:00 |
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David Harris
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43bc17350b
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Restored wally-busybear testbench now that graphical sim is working
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2021-06-18 12:36:25 -04:00 |
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bbracker
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72f1e3eab6
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buildroot added to regression because it passes regression
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2021-06-18 09:49:30 -04:00 |
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David Harris
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e03912f64c
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Cleaned up name of MTIME register in CSRC
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2021-06-18 07:53:49 -04:00 |
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bbracker
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832e4fc7e3
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making linux waveforms more useful
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2021-06-17 08:37:37 -04:00 |
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bbracker
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3e11da2aa2
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temporarily removing buildroot from regression until it is regenerated
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2021-06-07 13:20:50 -04:00 |
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David Harris
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95cc70295b
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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8bbabb683d
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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Ross Thompson
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6f58c66be8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-06-04 15:16:39 -05:00 |
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Ross Thompson
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e200b4b5a4
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Continued I-Cache cleanup.
Removed strange mux on InstrRawD along with
the select logic.
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2021-06-04 15:14:05 -05:00 |
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Ross Thompson
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35afdecda2
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Moved I-Cache offset selection mux to icache.sv (top level).
When we switch to set associative this is will be more efficient.
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2021-06-04 13:49:33 -05:00 |
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Katherine Parry
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19116ed889
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Double-precision FMA instructions
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2021-06-04 14:00:11 -04:00 |
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Ross Thompson
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2c16591396
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Reorganized the icache names.
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2021-06-04 12:53:42 -05:00 |
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David Harris
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a61411995a
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moved shared constants to a shared directory
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2021-06-03 22:41:30 -04:00 |
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bbracker
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8338b3bd34
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expanded GPIO testing and caught small GPIO bug
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2021-06-03 10:03:09 -04:00 |
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bbracker
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28abd28b1f
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fixed InstrValid signals and implemented less costly MEPC loading
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2021-06-02 10:03:19 -04:00 |
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bbracker
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a45b61ede9
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turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
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2021-05-28 23:11:37 -04:00 |
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bbracker
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142b02b30a
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improved PLIC test organization
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2021-05-21 15:13:02 -04:00 |
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Katherine Parry
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71e4a10efb
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FMV.D.X imperas test passes
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2021-05-20 22:17:59 -04:00 |
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bbracker
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114bba8370
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small bit of busybear debug progress
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2021-05-19 20:18:00 -04:00 |
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James E. Stine
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058b265d18
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Update rv64icfd batch script
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2021-05-18 16:01:53 -05:00 |
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David Harris
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5f214d60b6
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Removed rv64wally
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2021-05-18 14:08:46 -04:00 |
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David Harris
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433ea61d9e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/regression/vish_stacktrace.vstf
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2021-05-18 14:01:19 -04:00 |
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bbracker
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86d55cd07a
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fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions
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2021-05-17 19:25:54 -04:00 |
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bbracker
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69ef758e78
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regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench
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2021-05-17 18:44:47 -04:00 |
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David Harris
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1aa1908994
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Deleted vish_stacktrace
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2021-05-17 18:39:01 -04:00 |
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Elizabeth Hedenberg
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853c9243c1
|
commit ehedenberg coremark
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2021-05-17 18:02:35 -04:00 |
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James E. Stine
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8822bdd6ad
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Cleanup of regression
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2021-05-17 16:58:15 -05:00 |
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James E. Stine
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97cbdae674
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Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
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2021-05-17 16:48:51 -05:00 |
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Thomas Fleming
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a191978a97
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-05-14 07:40:08 -04:00 |
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Thomas Fleming
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1fc607b399
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Remove busy-mmu and fix missing signal
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2021-05-14 07:14:20 -04:00 |
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Jarred Allen
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dc41623754
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Minor fixes in regression
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2021-05-09 13:57:09 -04:00 |
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Jarred Allen
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788680fa4d
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Fix bug in regression script
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2021-05-06 12:56:57 -04:00 |
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Jarred Allen
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15da77fe15
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Clean up regression script and document it
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2021-05-04 18:58:59 -04:00 |
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Thomas Fleming
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d53afc8510
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-05-03 23:15:39 -04:00 |
|
Elizabeth Hedenberg
|
08bfaeffe3
|
coremark print statment
|
2021-05-03 19:35:08 -04:00 |
|
Elizabeth Hedenberg
|
81ed9b5d06
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coremark directory changes
|
2021-05-03 19:35:06 -04:00 |
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Ross Thompson
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21c0ee0cf2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-05-03 16:56:00 -05:00 |
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Ross Thompson
|
ed4f2ecb24
|
fixed subtle typo in icache fsm. Was messing up hit spill hit.
I believe the mibench qsort benchmark runs after this icache fix.
|
2021-05-03 16:55:36 -05:00 |
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Thomas Fleming
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3f7061d557
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-05-03 17:38:13 -04:00 |
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Jarred Allen
|
a21b84e2ad
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Add lint to regression
|
2021-05-03 17:32:05 -04:00 |
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Ross Thompson
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0a44d4dd4e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-05-03 14:53:54 -05:00 |
|
Ross Thompson
|
7185905f7b
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Reduced icache to 1 port memory.
|
2021-05-03 14:47:49 -05:00 |
|
Thomas Fleming
|
94d734cca9
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
|
2021-05-03 14:02:19 -04:00 |
|