Ross Thompson
5acdf541b9
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
9849983348
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
c985988867
Fixed a bug with the new cache flush changes.
2022-12-16 19:28:32 -06:00
Ross Thompson
9b9e954cc5
Cleanup comments.
2022-12-16 17:08:35 -06:00
Ross Thompson
5f556817c7
Further cleanfsm cleanup.
2022-12-16 16:37:45 -06:00
Ross Thompson
493b1a4280
More cachefsm cache flush cleanup.
2022-12-16 16:32:21 -06:00
Ross Thompson
3132246a46
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
698ca7d482
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-16 15:37:03 -06:00
Ross Thompson
91e64a0d67
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
ab3c5a0ca7
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
cturek
0ceecd9961
Added integer support for initC
2022-12-16 19:02:11 +00:00
cturek
9340a5eb49
Added mux for integer special case, renamed signals to match pipelined stage
2022-12-16 18:43:49 +00:00
David Harris
940fd2f924
Clean up interrupt masking by Commit
2022-12-16 08:27:39 -08:00
David Harris
a285f289a6
Disabled starting FPU divider when IDIV_ON_FPU = 0
2022-12-16 06:35:29 -08:00
cturek
9f1aa7ad19
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-12-16 03:41:39 +00:00
David Harris
da2d68c699
Use FlushE to reset integer divider FSM
2022-12-15 11:00:54 -08:00
David Harris
a8126458f6
Refactored stalls and flushes, including FDIV flush with FlushE
2022-12-15 10:56:18 -08:00
David Harris
3bef12b108
Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
2022-12-15 08:23:34 -08:00
Ross Thompson
8cd6a74c8f
Hazard cleanup.
2022-12-15 10:05:17 -06:00
Ross Thompson
c253b882be
Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.
2022-12-15 09:53:35 -06:00
Ross Thompson
0358a8d255
Merge branch 'main' into hazards
2022-12-15 08:44:59 -06:00
David Harris
e80e84aace
Added IDIV_ON_FPU flag to control whether integer division uses FPU
2022-12-15 06:37:55 -08:00
David Harris
643a2e7cf9
Use FPU divider for integer division when F is supported
2022-12-14 17:03:13 -08:00
cturek
482caec42d
Fixed BZero and initU/initUM muxes
2022-12-14 16:44:46 +00:00
Ross Thompson
4a0e4aed99
Signal renames to reflect figures.
2022-12-14 09:49:15 -06:00
Ross Thompson
8f04f2d9e7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-14 09:34:34 -06:00
Ross Thompson
b69aa39f30
Reduced complexity of linebytemask.
2022-12-14 09:34:29 -06:00
cturek
e4c1bb2bff
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-12-14 15:13:44 +00:00
Ross Thompson
0f0fed2496
Broken dont' use.
2022-12-11 23:24:01 -06:00
Ross Thompson
dbc3dac03d
Removed unused flushf.
2022-12-11 16:28:11 -06:00
Ross Thompson
ad7dd56180
Renamed CPUBusy to GatedStallF in IFU.
2022-12-11 15:54:19 -06:00
Ross Thompson
5b38b4e639
Renamed CPUBusy in LSU.
2022-12-11 15:52:51 -06:00
Ross Thompson
6d573b32d2
Changed CPUBusy to Stall in ebu modules.
2022-12-11 15:51:35 -06:00
Ross Thompson
232f866ad1
Renamed CPUBusy to Stall in cache.
2022-12-11 15:49:34 -06:00
Ross Thompson
a58fbd618e
Moved CPUBusy out of HPTW.
2022-12-11 15:48:00 -06:00
cturek
930fcbe956
Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
2022-12-10 21:56:35 +00:00
Ross Thompson
d3b2e331c2
Added comments about why it is not possible to use FlushWay and VictimWay directly.
2022-12-09 17:07:35 -06:00
Ross Thompson
f09b9e1572
Finished merge of kip and ross's ifu fix.
2022-12-09 16:52:22 -06:00
Ross Thompson
981ac3963a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-09 16:42:16 -06:00
Ross Thompson
1a24e7029f
Minor simplification of cacheway way selection muxes.
2022-12-09 16:42:05 -06:00
Kip Macsai-Goren
055ca9ee37
Addded fix for 32 bit periph test and added test to regression
2022-12-06 09:56:08 -08:00
Ross Thompson
5dbcf8fb10
Fixed bug Kip found.
...
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
2022-12-06 10:37:45 -06:00
Ross Thompson
1a9c932157
Renamed SelBusBuffer to SelFetchBuffer.
2022-12-05 17:51:13 -06:00
Ross Thompson
92066f81b6
Removed commented code.
2022-12-05 17:21:56 -06:00
Ross Thompson
37551ecc43
Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags.
2022-12-05 17:19:51 -06:00
Ross Thompson
dc31add951
Cache signal renames.
2022-12-04 16:09:09 -06:00
Ross Thompson
9bf0eedf73
Optimized way selection logic.
2022-12-04 12:30:56 -06:00
Ross Thompson
a130a96b45
Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.
2022-12-04 01:20:51 -06:00
Ross Thompson
3dea04e644
Moved selectedway mux into cacheway. It makes way more sense there.
2022-12-04 01:15:47 -06:00
Ross Thompson
f557150cae
Rename LineByteMux to FetchbufferbyteSel.
2022-12-04 01:00:04 -06:00
Ross Thompson
350fdd944d
Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."
...
This reverts commit fb221d7b64
2022-12-04 00:01:58 +00:00
cturek
fb221d7b64
Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
2022-12-02 21:44:29 +00:00
cturek
04ac350a29
Added flops to preproc
2022-12-02 20:31:08 +00:00
David Harris
3a07d56d33
Renamed FPUStallD to FCvtIntStallD
2022-12-02 11:55:23 -08:00
David Harris
1b0f878c16
Renamed DivStartE to IFDivStartE
2022-12-02 11:30:49 -08:00
David Harris
db5f3c15a4
FPU divider working with execute stage stall
2022-12-02 11:11:53 -08:00
Ross Thompson
3442b04f9e
Properly flush cacheLRU.
2022-12-01 17:32:58 -06:00
Ross Thompson
e403800ce8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-01 11:47:54 -06:00
Ross Thompson
5025664cb0
Removed unused port on cacheway.
2022-12-01 11:47:48 -06:00
David Harris
28996d0b12
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-01 08:15:51 -08:00
David Harris
1bd639be6d
code cleanup
2022-12-01 08:15:48 -08:00
Ross Thompson
e6bd86f4fa
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-30 17:19:04 -06:00
David Harris
4ddc8fd603
signal sufixes in integer division
2022-11-30 15:15:37 -08:00
Ross Thompson
a6355b1dcb
More optimization.
2022-11-30 11:26:48 -06:00
Ross Thompson
0aa7ce0b24
Removed reset on dirty cache bits.
2022-11-30 11:04:37 -06:00
Ross Thompson
cedb234013
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
2022-11-30 11:01:25 -06:00
Ross Thompson
0454eb95ad
Preparing to merge dirty and tag srams.
2022-11-30 10:40:48 -06:00
Ross Thompson
de538d1c2f
Intermediate commit. Replaced flip flop dirty bit array with sram.
2022-11-30 00:08:31 -06:00
Ross Thompson
453ea36512
Optimization of cacheway.
2022-11-29 18:30:47 -06:00
Ross Thompson
fbf543bf57
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
b5718c9baa
Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
2022-11-29 14:51:09 -06:00
Ross Thompson
96cc4c7ebe
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
78acd40424
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
6dd5668d21
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-22 18:07:32 -06:00
cturek
bdb9e24a66
Almost done with Int division
2022-11-22 22:22:59 +00:00
Ross Thompson
279f5bc615
Cleanup cacheLRU.
2022-11-22 14:59:01 -06:00
Ross Thompson
e1dbe58632
File name change for cachereplacement policy to cacheLRU
2022-11-20 22:35:02 -06:00
Ross Thompson
4e926ba4cf
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
00218d559f
Missing a file. Last commit will fail.
2022-11-17 17:45:41 -06:00
Ross Thompson
0106777f02
Finally have the correct replacement policy implementation.
2022-11-17 17:36:37 -06:00
Ross Thompson
faa13a96e0
I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
2022-11-16 15:38:37 -06:00
Ross Thompson
22ad49eef2
Progress on the cache replacement policy implementation.
2022-11-16 15:35:34 -06:00
Ross Thompson
0796cd92fc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-16 12:42:29 -06:00
Ross Thompson
42111db671
Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
2022-11-16 12:36:58 -06:00
David Harris
59335ac70f
comment cleanup
2022-11-16 10:23:20 -08:00
David Harris
be9c618c94
Renamed DivBusy to FDivBusyE in FPU
2022-11-16 10:13:27 -08:00
David Harris
128cc86254
Moved DivStartE to fdivsqrtfsm
2022-11-16 10:00:07 -08:00
Ross Thompson
1f21a2bab1
Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.
2022-11-16 11:15:34 -06:00
cturek
ffd03e9548
Attempt to fix FPGA synth errors
2022-11-15 20:34:28 +00:00
cturek
98b66aab9f
Fixed lint errors in postprocessing
2022-11-15 20:31:23 +00:00
Ross Thompson
3df51716b1
Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state.
2022-11-14 16:02:20 -06:00
Ross Thompson
b53f8eceef
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
284b97aff6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-14 13:48:56 -06:00
David Harris
6372139af4
Removed comment about nonexistent possible bug
2022-11-14 09:56:33 -08:00
David Harris
06dbed92c8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-14 09:52:24 -08:00
David Harris
f9202187ba
Removed comment about nonexistent possible bug
2022-11-14 09:52:21 -08:00
Ross Thompson
13e6f7d80b
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
cturek
abaa33b92a
Added majority of combinational logic
2022-11-14 00:06:38 +00:00
cturek
6740d77b63
Added Quotient/Remainder calcs to normal termination
2022-11-13 23:44:34 +00:00
cturek
12e3646153
Added flops for n and m, added B=0 signal
2022-11-13 23:02:43 +00:00
