Ross Thompson 493b1a4280 More cachefsm cache flush cleanup.		2022-12-16 16:32:21 -06:00
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cache	More cachefsm cache flush cleanup.	2022-12-16 16:32:21 -06:00
ebu	Rough draft of cache flush fsm enhancement.	2022-12-16 15:28:22 -06:00
fpu	Added integer support for initC	2022-12-16 19:02:11 +00:00
generic	Intermediate commit. Replaced flip flop dirty bit array with sram.	2022-11-30 00:08:31 -06:00
hazard	Refactored stalls and flushes, including FDIV flush with FlushE	2022-12-15 10:56:18 -08:00
ieu	Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.	2022-12-15 09:53:35 -06:00
ifu	Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.	2022-12-15 09:53:35 -06:00
lsu	Renamed CPUBusy in LSU.	2022-12-11 15:52:51 -06:00
mmu	Moved CPUBusy out of HPTW.	2022-12-11 15:48:00 -06:00
muldiv	Use FlushE to reset integer divider FSM	2022-12-15 11:00:54 -08:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Clean up interrupt masking by Commit	2022-12-16 08:27:39 -08:00
uncore	Fixed the uart transmit fifo overrun bug.	2022-10-26 14:48:09 -05:00
wally	Use FlushE to reset integer divider FSM	2022-12-15 11:00:54 -08:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00