Thomas Fleming
ca2a65770c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 15:46:51 -05:00
Noah Boorstin
f0a103687e
Merge branch 'main' into busybear
2021-03-05 20:27:19 +00:00
Noah Boorstin
6981907521
fix wally-pipelined-batch.do to match wally-pipelined.do
2021-03-05 20:27:01 +00:00
bbracker
612f7a9ee4
added a delay to sel signals
2021-03-05 15:07:34 -05:00
bbracker
a1223ee13b
more merging fixes
2021-03-05 14:36:07 -05:00
bbracker
2cd0f19129
remove deprecated mem signals
2021-03-05 14:27:38 -05:00
bbracker
420c9a11c2
refactored sim file
2021-03-05 14:25:16 -05:00
bbracker
62dd9e3075
first merge of ahb fix
2021-03-05 14:24:22 -05:00
Noah Boorstin
464c1de03d
busybear: slight testbench update
2021-03-05 19:00:40 +00:00
Thomas Fleming
97e9baa316
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 13:35:44 -05:00
Thomas Fleming
85dcbee86b
Place tlb parameters into constant header file
2021-03-05 13:35:24 -05:00
Thomas Fleming
e48dc38869
Export SATP_REGW from csrs to MMU modules
2021-03-05 01:22:53 -05:00
Noah Boorstin
0af002eb2f
busybear: make CSRs only weird for us
2021-03-05 00:46:32 +00:00
Noah Boorstin
7208b9bcf2
busybear: better implenetation of sim-busybear-batch
2021-03-05 00:39:03 +00:00
Ross Thompson
a982ad7a9a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-04 17:31:27 -06:00
Ross Thompson
7902c3fdb6
updated the function radix to look at wally signals.
2021-03-04 17:31:12 -06:00
Noah Boorstin
cfcd7d1518
busybear: make imperas tests work again
2021-03-04 22:44:49 +00:00
Katherine Parry
5374dca1b9
fixed various bugs
2021-03-04 22:20:39 +00:00
Katherine Parry
4591b25c86
fixed various bugs
2021-03-04 22:20:28 +00:00
Katherine Parry
6fa2bc8efe
fixed various bugs
2021-03-04 22:20:23 +00:00
Katherine Parry
10b179399c
fixed various bugs
2021-03-04 22:20:02 +00:00
Katherine Parry
8e3b74c772
fixed various bugs
2021-03-04 22:19:21 +00:00
Katherine Parry
4e6b35c8b2
fixed various bugs
2021-03-04 22:18:47 +00:00
Katherine Parry
3c86d0912a
fixed various bugs
2021-03-04 22:18:19 +00:00
Thomas Fleming
38bd683f2d
Merge branch 'walker' into main
2021-03-04 15:27:03 -05:00
Noah Boorstin
5c456e2d7f
busybear: comment out instraccessfaultf for imem for now
2021-03-04 20:26:41 +00:00
Noah Boorstin
fde94f9057
Merge branch 'main' into busybear
...
Conflicts:
wally-pipelined/src/uncore/imem.sv
2021-03-04 20:16:03 +00:00
Ross Thompson
619bbd9d83
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Ross Thompson
a8cd4f2b2e
Fixed forwarding around the 2 bit predictor.
2021-03-04 13:01:41 -06:00
Shreya Sanghai
f95a1eadd9
fixed bugs
2021-03-04 12:59:45 -05:00
Shreya Sanghai
7cd8f1a592
added performance counters
2021-03-04 11:42:52 -05:00
bbracker
7852d866ef
JALR testing
2021-03-04 10:37:30 -05:00
Ross Thompson
d0223da2f7
Converted to using the BTB to predict the instruction class.
2021-03-04 09:23:35 -06:00
Thomas Fleming
8c410b6fbe
Install dtlb in dmem
2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5
Install tlb into ifu
2021-03-04 03:11:34 -05:00
Thomas Fleming
ab6ae6d3f1
Merge branch 'tlb_toy' into main
2021-03-04 02:41:11 -05:00
Thomas Fleming
7a9f866120
Move tlb into mmu directory
2021-03-04 02:39:08 -05:00
Teo Ene
b15ef47d24
Fix to 32-bit option of commit 2d40898158
2021-03-04 01:33:34 -06:00
Thomas Fleming
d821a1dbfa
Merge branch 'main' into tlb_toy
2021-03-04 01:18:04 -05:00
Thomas Fleming
c03b540956
Generalize tlb module
...
- number of tlb entries is now parameterized
- tlb now supports rv64i
2021-03-04 01:13:31 -05:00
Thomas Fleming
692d4152fa
Begin hardware page table walker
2021-03-03 17:13:45 -05:00
Thomas Fleming
5fd521d333
Create virtual memory ad-hoc test
...
Test program is currently failing on ovpsim. There is no indication that ovpsim
is properly implementing virtual memory translation when satp is set accordingly.
Need to confirm whether this is a problem with ovpsim, how ovpsim is being
called, or the test itself.
2021-03-03 17:06:37 -05:00
Teo Ene
d3a1afe50e
Fix to last push
2021-03-03 15:20:38 -06:00
Teo Ene
b50faef94d
Updated coremark .do file for easier debugging
2021-03-03 15:10:39 -06:00
Teo Ene
e30645a4f1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-02 17:23:44 -06:00
Teo Ene
d02e22feac
Updated coremark .do file for easier debugging
2021-03-02 17:23:39 -06:00
Noah Boorstin
beb2beabfd
busybear: add sim-busybear and sim-busybear-batch based on sim-wally
2021-03-01 21:01:15 +00:00
Noah Boorstin
923489fe16
busybear: probably discovered bug in ahb code
2021-03-01 20:56:04 +00:00
Noah Boorstin
b6dc0a8707
busybear: only check pc when it actually changes
2021-03-01 19:08:35 +00:00
Noah Boorstin
b3247eadd2
busybear: more adapting to new memory system
2021-03-01 18:50:42 +00:00
Noah Boorstin
f11b3108d8
busybear: fix bootram range
2021-03-01 17:45:21 +00:00
David Harris
23a1cf63b3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-01 00:09:55 -05:00
David Harris
6f4e8b723e
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Teo Ene
2d40898158
Properly implemented the fix from commit 5fee65231e
2021-02-28 22:22:04 -06:00
Noah Boorstin
a267115635
Merge branch 'main' into busybear
2021-02-28 20:45:08 +00:00
Noah Boorstin
17715085ba
busybear: start preloading bootmem
2021-02-28 20:43:57 +00:00
Noah Boorstin
932bc0ef85
busybear: check instead of providing InstrF
2021-02-28 16:46:53 +00:00
Noah Boorstin
856a1079cc
busybear: change sstatus, mstatus reset value
2021-02-28 16:19:03 +00:00
Noah Boorstin
2769b147cb
busybear: add 2nd dtim for bootram
2021-02-28 16:08:54 +00:00
Noah Boorstin
969c094489
busybear: remove gpio, start adding 2nd ram
2021-02-28 06:02:40 +00:00
Noah Boorstin
0596d61a2a
busybear: instantiate normal wallypipelinedsoc
2021-02-28 06:02:21 +00:00
Ross Thompson
6191fcb1af
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
Ross Thompson
c2cf3f9fb6
Updating the test bench to include a function radix. Not done.
2021-02-26 19:43:40 -06:00
David Harris
73920282af
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
0258901865
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
kaveh pezeshki
e8b306bcba
merged with main to integrate with AHB
2021-02-26 05:37:10 -08:00
Noah Boorstin
4c7b185d90
busybear: add main ram loading, better instr checking also
2021-02-26 20:26:54 +00:00
kaveh Pezeshki
2782ca2480
fixed sensitivity list on error checking always block, removed useless once and for all
2021-02-26 13:41:16 -05:00
kaveh pezeshki
adadc21fc6
restored
2021-02-26 02:22:08 -08:00
David Harris
225102047a
Clean up bus interface code
2021-02-26 01:03:47 -05:00
David Harris
1b61d78ac2
Retimed peripherals for AHB interface
2021-02-26 00:55:41 -05:00
David Harris
bad180fc15
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-25 15:49:38 -05:00
David Harris
f57096a5d2
Restored to working multiplier after Lab 2
2021-02-25 15:32:43 -05:00
Brett Mathis
b0a5052bcf
FPU Assembly tests
2021-02-25 14:32:36 -06:00
Teo Ene
a35fdac75b
Fixed previous commit
2021-02-25 11:24:44 -06:00
Teo Ene
5fee65231e
Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.
2021-02-25 11:23:01 -06:00
Teo Ene
b9701293a0
Changed TIMBASE in coremark config file
2021-02-25 11:03:41 -06:00
Teo Ene
8491deb1a9
Changed .do file back to run all
2021-02-25 09:58:54 -06:00
David Harris
cd4ba8831c
Merged bus into main
2021-02-25 00:28:41 -05:00
Teo Ene
cfd45a46c3
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
kaveh pezeshki
251aa982eb
condensed always blocks to avoid race conditions
2021-02-24 11:35:28 -08:00
Noah Boorstin
ddaf67c043
busybear: preload bootram
...
thanks to Prof Stine for the .do file commands
@kaveh can you check line 201? it does nothing, but things break when
I remove that line
2021-02-24 18:46:09 +00:00
David Harris
38b8cc652c
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
kaveh pezeshki
06f73fe5fe
added comments for RAM and bootram, removed trailing whitepace
2021-02-23 21:28:33 -08:00
Noah Boorstin
b7f4e72eec
busybear: add bootram section in the same manner as ram
2021-02-24 02:02:28 +00:00
Noah Boorstin
914a36e3e8
busybear: add support for subwords in ram
...
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
2021-02-24 01:51:18 +00:00
Noah Boorstin
7b7e87bd0b
busybear: start adding ram
2021-02-23 22:01:23 +00:00
Katherine Parry
07641203ee
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-23 20:21:53 +00:00
Katherine Parry
906ec30339
inital FMA push
2021-02-23 20:19:12 +00:00
Noah Boorstin
5394d38e4a
busybear: remove unused signals
2021-02-23 19:38:19 +00:00
Noah Boorstin
c42c485377
busybear: instantiate soc instead of hart
2021-02-23 18:59:06 +00:00
David Harris
7737b0f709
Fixed fetch stall after jump in bus unit
2021-02-23 09:08:57 -05:00
David Harris
f372e2b8e8
Debugging Bus interface
2021-02-22 13:48:30 -05:00
kaveh pezeshki
e146946e58
Merge remote-tracking branch 'origin/tlb_toy' into busybear
2021-02-22 02:23:01 -08:00
Ross Thompson
c856003f73
RAS needs to be reset or preloaded. For now I just reset it.
...
Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
597dd1e7e6
Added FlushF to hazard unit.
...
Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
06e975ac2f
minor change to wave file.
2021-02-19 09:08:13 -06:00
Ross Thompson
7d6093b302
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
...
About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
Thomas Fleming
ca51e7ca1c
Create simple TLB
...
This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
2021-02-18 18:06:09 -05:00
David Harris
87ad559a90
Updated creation date of mul
2021-02-18 08:13:08 -05:00
