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Author SHA1 Message Date
Rose Thompson
c77a47b403 Output the instruction trace to the logs directory. 2023-11-21 13:47:58 -06:00
Rose Thompson
d57ec045de Merge branch 'main' of github.com:ross144/cvw 2023-11-21 13:46:45 -06:00
Rose Thompson
f82f7d9323 Updated qemu scripts for updated linux build. 
expanded memory from 128MB to 256MB.
 2023-11-21 13:46:37 -06:00
Rose Thompson
b02bd6c835 Finally we got the wally tracer working with linux. 2023-11-21 13:45:55 -06:00
Rose Thompson
3fd6d3464c We are logging now. 2023-11-21 13:02:34 -06:00
Rose Thompson
6ff8d19157 Added code to the wallyTracer to support outputing an instruction trace. 2023-11-21 12:28:19 -06:00
Rose Thompson
58d89cc347 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-21 10:48:05 -06:00
Rose Thompson
add7fecb72 Merge branch 'main' of github.com:ross144/cvw 2023-11-21 10:40:01 -06:00
Rose Thompson
386cf3eb56 Merge pull request #493 from stineje/main 
marchid approved by RISC-V
 2023-11-21 08:33:07 -08:00
Rose Thompson
24536fb1c6 Merge pull request #492 from davidharrishmc/dev 
Clean up unused signals, other cleanup
 2023-11-21 08:32:19 -08:00
James E. Stine
776eec16ae Update ppaAnalyze for recent update to put back parsing name 2023-11-21 09:24:07 -06:00
James E. Stine
141cbd3f9f Update marchid/mvendorid for CV-Wally 2023-11-21 09:23:02 -06:00
David Harris
2b2016271a repo cleanup and start to add CMO tests 2023-11-20 23:41:36 -08:00
David Harris
d3ce683e06 Removed other unused signals from Verilog 2023-11-20 23:37:56 -08:00
David Harris
f89fd8a7fe removed unused cache signals 2023-11-20 23:16:35 -08:00
Rose Thompson
1acc3951c8 More simplifications. 2023-11-21 00:19:24 -06:00
Rose Thompson
1d811b085c More cleanup. 2023-11-21 00:14:59 -06:00
Rose Thompson
d2a747bf3d cleanup. 2023-11-20 23:59:40 -06:00
Rose Thompson
70eb110a9c More optimizations to simplify cmo logic. 2023-11-20 22:13:31 -06:00
Rose Thompson
52ac07ce8d Removed the CMO_WRITEBACK state from the cache and unused signals. 2023-11-20 20:56:30 -06:00
Rose Thompson
5fb3c83efc Removed the CMO_WRITEBACK state from the cache. 2023-11-20 20:52:11 -06:00
Rose Thompson
667fe035c0 Simplified CMO.Zero fsm implementation slightly. 2023-11-20 17:01:43 -06:00
David Harris
739c7f3f1c Merge pull request #491 from ross144/main 
Running ImperasDV Linux is upto date
 2023-11-20 10:28:05 -08:00
Rose Thompson
eed6f11df6 Merge branch 'main' of github.com:ross144/cvw 2023-11-20 11:29:45 -06:00
Rose Thompson
23e05cb8b2 Finally have the cbo way muxing controls reduced to something sane. 2023-11-20 11:28:03 -06:00
Rose Thompson
b137759b45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-20 10:34:36 -06:00
Rose Thompson
64e627841a Merge branch 'main' of github.com:ross144/cvw 2023-11-20 10:30:42 -06:00
Rose Thompson
3594c08d4b Modified linux imperas tests to 
1. enable zicclsm
2. enable logging at 7000 ms
 2023-11-20 10:30:35 -06:00
Rose Thompson
17e91f31f6 Merge pull request #490 from davidharrishmc/dev 
Synthesis running for textbook, preload IROM to avoid it being optimized out, updated M tests in risk-arch-test
 2023-11-19 20:42:29 -08:00
David Harris
8cb433cb66 Commented IROM preloading 2023-11-19 19:33:57 -08:00
Rose Thompson
cdd21d6635 Added menvcfg to debugger for checking what linux has configured. 2023-11-19 13:44:22 -06:00
David Harris
6fd32b6643 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-19 06:49:25 -08:00
David Harris
887cf935dc wallySynthAll.sh automates running all synthesis experiments without maxopt 2023-11-19 06:49:07 -08:00
David Harris
b692c913c4 Changed rv32gc to do IDIV in MDU and have k=2 copies of FDIV stages; added correct sky130 adder data; fixed feature substitution in synthesis makefile 2023-11-18 20:56:50 -08:00
David Harris
acd8a63628 Merge pull request #489 from ross144/main 
fixes issue #487
 2023-11-18 19:22:33 -08:00
Rose Thompson
4ad7afcbf2 Merge pull request #488 from JacobPease/main 
FPGA Bootloader Preload From File
 2023-11-18 17:24:52 -08:00
Jacob Pease
a1e7158bd9 Merge branch 'main' of github.com:openhwgroup/cvw 2023-11-18 19:20:48 -06:00
Jacob Pease
87e6a5ccf2 Updated ROM to preload bootloader from file and infer a block ram when building for FPGA. 2023-11-18 19:15:39 -06:00
Rose Thompson
efcd09c6cd Merge branch 'main' of github.com:ross144/cvw 2023-11-18 19:01:48 -06:00
Rose Thompson
8cbd3de413 Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data. 2023-11-18 19:01:39 -06:00
Rose Thompson
4429732e8f Merge pull request #485 from davidharrishmc/dev 
Wally sweep running again, embench sweep across configs
 2023-11-17 21:42:12 -08:00
David Harris
acc2db256f turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep 2023-11-17 20:25:24 -08:00
David Harris
96556064a4 Restored RV64GC BPRED_SIZE=10 for consistent synthesis results 2023-11-17 18:31:44 -08:00
David Harris
423ae2bb76 Ignore benchmark results 2023-11-17 17:02:32 -08:00
David Harris
96f9409da4 Embench Makefile to sweep experiments across configs 2023-11-17 15:11:52 -08:00
David Harris
7b33331cf7 Got Wally sweep running again 2023-11-17 15:10:57 -08:00
David Harris
c500a7c057 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-17 14:26:55 -08:00
David Harris
0eb23569f5 Merge pull request #480 from stineje/main 
wrapper insertion automatically for Wally vs. individual PPA analysis
 2023-11-17 14:26:47 -08:00
James E. Stine
3dc7b93f57 Revert removal of WRAPPER option that is not prudent 2023-11-17 16:25:35 -06:00
David Harris
44ec6efdab Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-17 13:28:07 -08:00