mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 10:15:19 +00:00
Merge branch 'main' of github.com:ross144/cvw
This commit is contained in:
Rose Thompson
commit
d57ec045de
@ -1 +1 @@
|
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Subproject commit 4c5eb87983f51ca7fcf7855306877b3d1c3aabf1
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Subproject commit 54fd9a0f10aabc662991567ca19ff3e61bfd3939
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@ -10,8 +10,7 @@ from datetime import datetime
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import re
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import collections
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#archs = ["rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr", "rv32imafdc_zba_zbb_zbc_zbs_zicsr"]
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archs = ["rv32imafdc_zba_zbb_zbc_zbs_zicsr", "rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr"]
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archs = ["rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr", "rv32imafdc_zba_zbb_zbc_zbs_zicsr"]
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def calcgeomean(d, arch):
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progs = ["aha-mont64", "crc32", "cubic", "edn", "huffbench", "matmult-int", "minver", "nbody", "nettle-aes", "nettle-sha256", "nsichneu", "picojpeg", "qrduino", "sglib-combined", "slre", "st", "statemate", "ud", "wikisort"]
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@ -24,7 +23,8 @@ def calcgeomean(d, arch):
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return result
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def tabulate_arch_sweep(directory):
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for case in ["wallySizeOpt_size", "wallySpeedOpt_speed"]:
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for case in ["wallySizeOpt_size", "wallySpeedOpt_size", "wallySizeOpt_speed", "wallySpeedOpt_speed"]:
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print(case)
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d = collections.defaultdict(dict)
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for arch in archs:
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file = case+"_"+arch+".json"
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@ -60,7 +60,7 @@ def tabulate_arch_sweep(directory):
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for arch in archs:
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geomean = calcgeomean(d, arch)
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print(geomean, end="\t")
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print("")
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print("\n\n")
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def run_arch_sweep():
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# make a folder whose name depends on the date
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@ -83,5 +83,5 @@ def run_arch_sweep():
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return dir
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directory = run_arch_sweep()
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#directory = "run_20231117_082325"
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#directory = "run_20231120_072037-caches"
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tabulate_arch_sweep(directory)
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@ -100,7 +100,7 @@ localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
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localparam BOOTROM_PRELOAD = 1'b1;
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localparam UNCORE_RAM_SUPPORTED = 1'b1;
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localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
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localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
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localparam logic [63:0] UNCORE_RAM_RANGE = 64'h0FFFFFFF;
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localparam UNCORE_RAM_PRELOAD = 1'b1;
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localparam EXT_MEM_SUPPORTED = 1'b0;
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localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
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21
src/cache/cache.sv
vendored
21
src/cache/cache.sv
vendored
@ -35,7 +35,6 @@ module cache import cvw::*; #(parameter cvw_t P,
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input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations)
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// cpu side
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input logic [1:0] CacheRW, // [1] Read, [0] Write
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input logic [1:0] CacheAtomic, // Atomic operation
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input logic FlushCache, // Flush all dirty lines back to memory
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input logic InvalidateCache, // Clear all valid bits
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input logic [3:0] CMOp, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
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@ -90,18 +89,16 @@ module cache import cvw::*; #(parameter cvw_t P,
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logic [NUMWAYS-1:0] FlushWay, NextFlushWay;
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logic FlushWayCntEn;
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logic SelWriteback;
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logic SelCMOWriteback;
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logic SelBothWriteback;
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logic LRUWriteEn;
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logic SelFlush;
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logic ResetOrFlushCntRst;
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logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache;
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logic SelFetchBuffer;
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logic CacheEn;
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logic SelWay;
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logic [LINELEN/8-1:0] LineByteMask;
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logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
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logic ZeroCacheLine;
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logic CMOZeroHit;
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logic [LINELEN-1:0] PreLineWriteData;
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genvar index;
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@ -119,15 +116,15 @@ module cache import cvw::*; #(parameter cvw_t P,
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// Array of cache ways, along with victim, hit, dirty, and read merging logic
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cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
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.clk, .reset, .CacheEn, .CMOp, .CacheSet, .PAdr, .LineWriteData, .LineByteMask,
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.SetValid, .ClearValid, .SetDirty, .ClearDirty, .CMOZeroHit, .SelWriteback, .SelCMOWriteback, .VictimWay,
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.clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, .SelWay,
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.SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay,
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.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache);
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// Select victim way for associative caches
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if(NUMWAYS > 1) begin:vict
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cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
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.clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn,
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.SetValid, .ClearValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache);
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.SetValid, .ClearValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
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end else
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assign VictimWay = 1'b1; // one hot.
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@ -156,11 +153,10 @@ module cache import cvw::*; #(parameter cvw_t P,
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.PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord);
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// Bus address for fetch, writeback, or flush writeback
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assign SelBothWriteback = SelWriteback | SelCMOWriteback;
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mux3 #(PA_BITS) CacheBusAdrMux(.d0({PAdr[PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
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.d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
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.d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}),
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.s({SelFlush, SelBothWriteback}), .y(CacheBusAdr));
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.s({SelFlush, SelWriteback}), .y(CacheBusAdr));
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Write Path
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@ -171,7 +167,6 @@ module cache import cvw::*; #(parameter cvw_t P,
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assign PreLineWriteData = FetchBuffer;
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end
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if(!READ_ONLY_CACHE) begin:WriteSelLogic
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logic [CACHEWORDSPERLINE-1:0] MemPAdrDecoded;
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logic [LINELEN/8-1:0] DemuxedByteMask, FetchBufferByteSel;
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// Adjust byte mask from word to cache line
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@ -229,10 +224,10 @@ module cache import cvw::*; #(parameter cvw_t P,
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/////////////////////////////////////////////////////////////////////////////////////////////
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cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
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.FlushStage, .CacheRW, .CacheAtomic, .Stall,
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.FlushStage, .CacheRW, .Stall,
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.CacheHit, .LineDirty, .CacheStall, .CacheCommitted,
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.CacheMiss, .CacheAccess, .SelAdr,
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.ClearDirty, .SetDirty, .SetValid, .ClearValid, .ZeroCacheLine, .CMOZeroHit, .SelWriteback, .SelCMOWriteback, .SelFlush,
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.CacheMiss, .CacheAccess, .SelAdr, .SelWay,
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.ClearDirty, .SetDirty, .SetValid, .ClearValid, .ZeroCacheLine, .SelWriteback, .SelFlush,
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.FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
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.FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
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.InvalidateCache, .CMOp, .CacheEn, .LRUWriteEn);
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1
src/cache/cacheLRU.sv
vendored
1
src/cache/cacheLRU.sv
vendored
@ -41,7 +41,6 @@ module cacheLRU
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input logic SetValid, // Set the dirty bit in the selected way and set
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input logic ClearValid, // Clear the dirty bit in the selected way and set
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input logic InvalidateCache, // Clear all valid bits
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input logic FlushCache, // Flush all dirty lines back to memory
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output logic [NUMWAYS-1:0] VictimWay // LRU selects a victim to evict
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);
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52
src/cache/cachefsm.sv
vendored
52
src/cache/cachefsm.sv
vendored
@ -38,7 +38,6 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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output logic CacheStall, // Cache stalls pipeline during multicycle operation
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// inputs from IEU
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input logic [1:0] CacheRW, // [1] Read, [0] Write
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input logic [1:0] CacheAtomic, // Atomic operation
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input logic FlushCache, // Flush all dirty lines back to memory
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input logic InvalidateCache, // Clear all valid bits
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input logic [3:0] CMOp, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
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@ -60,11 +59,10 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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output logic SetDirty, // Set the dirty bit in the selected way and set
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output logic ClearDirty, // Clear the dirty bit in the selected way and set
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output logic ZeroCacheLine, // Write zeros to all bytes of cacheline
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output logic CMOZeroHit, // CMOZ hit
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output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback
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output logic SelCMOWriteback, // Overrides cached tag check to select a specific way and set for writeback for both data and tag
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output logic LRUWriteEn, // Update the LRU state
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output logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
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output logic SelWay, // Controls which way to select a way data and tag, 00 = hitway, 10 = victimway, 11 = flushway
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output logic FlushAdrCntEn, // Enable the counter for Flush Adr
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output logic FlushWayCntEn, // Enable the way counter during a flush
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output logic FlushCntRst, // Reset both flush counters
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@ -77,6 +75,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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logic AnyMiss;
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logic FlushFlag;
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logic CMOWritebackHit;
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logic CMOWriteback;
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logic CMOZeroNoEviction;
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logic CMOZeroEviction;
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@ -88,10 +87,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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STATE_READ_HOLD, // required for back to back reads. structural hazard on writting SRAM
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// flush cache
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STATE_FLUSH,
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STATE_FLUSH_WRITEBACK,
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// CMO states
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STATE_CMO_WRITEBACK,
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STATE_CMO_DONE
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STATE_FLUSH_WRITEBACK
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} statetype;
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statetype CurrState, NextState;
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@ -102,6 +98,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit;
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assign CMOZeroNoEviction = CMOp[3] & ~LineDirty; // (hit or miss) with no writeback store zeros now
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assign CMOZeroEviction = CMOp[3] & LineDirty; // (hit or miss) with writeback dirty line
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assign CMOWriteback = CMOWritebackHit | CMOZeroEviction;
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assign FlushFlag = FlushAdrFlag & FlushWayFlag;
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@ -124,8 +121,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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STATE_READY: if(InvalidateCache) NextState = STATE_READY; // exclusion-tag: dcache InvalidateCheck
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else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH;
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else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement
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else if(AnyMiss | CMOZeroEviction) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
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else if(CMOWritebackHit) NextState = STATE_CMO_WRITEBACK;
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else if(AnyMiss | CMOWriteback) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
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else NextState = STATE_READY;
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STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE;
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else if(CacheBusAck) NextState = STATE_READY;
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@ -134,8 +130,9 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
|
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STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD;
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else NextState = STATE_READY;
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// exclusion-tag-start: icache case
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STATE_WRITEBACK: if(CacheBusAck & ~CMOp[3]) NextState = STATE_FETCH;
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else if(CacheBusAck) NextState = STATE_CMO_DONE;
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STATE_WRITEBACK: if (CacheBusAck & (CMOp[1] | CMOp[2])) NextState = STATE_READ_HOLD;
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else if(CacheBusAck & ~CMOp[3]) NextState = STATE_FETCH;
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else if(CacheBusAck) NextState = STATE_READ_HOLD;
|
||||
else NextState = STATE_WRITEBACK;
|
||||
// eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
|
||||
STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK;
|
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@ -144,32 +141,25 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
|
||||
STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH;
|
||||
else if(CacheBusAck) NextState = STATE_READ_HOLD;
|
||||
else NextState = STATE_FLUSH_WRITEBACK;
|
||||
|
||||
STATE_CMO_WRITEBACK: if(CacheBusAck & (CMOp[1] | CMOp[2])) NextState = STATE_CMO_DONE;
|
||||
else NextState = STATE_CMO_WRITEBACK;
|
||||
STATE_CMO_DONE: if(Stall) NextState = STATE_CMO_DONE;
|
||||
else NextState = STATE_READY;
|
||||
// exclusion-tag-end: icache case
|
||||
default: NextState = STATE_READY;
|
||||
endcase
|
||||
end
|
||||
|
||||
// com back to CPU
|
||||
assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & (CurrState == STATE_READ_HOLD | CurrState == STATE_CMO_DONE));
|
||||
assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss | CMOWritebackHit | CMOZeroEviction)) | // exclusion-tag: icache StallStates
|
||||
assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & (CurrState == STATE_READ_HOLD));
|
||||
assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss | CMOWriteback)) | // exclusion-tag: icache StallStates
|
||||
(CurrState == STATE_FETCH) |
|
||||
(CurrState == STATE_WRITEBACK) |
|
||||
(CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
|
||||
(CurrState == STATE_FLUSH) |
|
||||
(CurrState == STATE_FLUSH_WRITEBACK) |
|
||||
(CurrState == STATE_CMO_WRITEBACK);
|
||||
(CurrState == STATE_FLUSH_WRITEBACK);
|
||||
// write enables internal to cache
|
||||
assign CMOZeroHit = CurrState == STATE_READY & CMOp[3] & CacheHit ;
|
||||
assign SetValid = CurrState == STATE_WRITE_LINE |
|
||||
(CurrState == STATE_READY & CMOZeroNoEviction) |
|
||||
(P.ZICBOZ_SUPPORTED & CurrState == STATE_READY & CMOZeroNoEviction) |
|
||||
(P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CacheBusAck & CMOp[3]);
|
||||
assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0] & CacheHit) |
|
||||
(CurrState == STATE_CMO_WRITEBACK & CMOp[2] & CacheBusAck));
|
||||
(CurrState == STATE_WRITEBACK & CMOp[2] & CacheBusAck));
|
||||
// coverage off -item e 1 -fecexprrow 8
|
||||
assign LRUWriteEn = (((CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
|
||||
(CurrState == STATE_WRITE_LINE)) & ~FlushStage) |
|
||||
@ -181,13 +171,14 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
|
||||
assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) | // exclusion-tag: icache ClearDirty
|
||||
(CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set.
|
||||
// Flush and eviction controls
|
||||
(P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck);
|
||||
(P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck);
|
||||
assign SelWay = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOp[1] | CMOp[2])) | (P.ZICBOZ_SUPPORTED & CacheBusAck & CMOp[3]))) |
|
||||
(CurrState == STATE_READY & ((AnyMiss & LineDirty) | (P.ZICBOZ_SUPPORTED & CMOZeroNoEviction & ~CacheHit))) |
|
||||
(CurrState == STATE_WRITE_LINE);
|
||||
assign ZeroCacheLine = P.ZICBOZ_SUPPORTED & ((CurrState == STATE_READY & CMOZeroNoEviction) |
|
||||
(CurrState == STATE_WRITEBACK & (CMOp[3] & CacheBusAck)));
|
||||
assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
|
||||
(CurrState == STATE_READY & AnyMiss & LineDirty);
|
||||
assign SelCMOWriteback = CurrState == STATE_CMO_WRITEBACK;
|
||||
|
||||
assign SelWriteback = (CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | ~CacheBusAck)) |
|
||||
(CurrState == STATE_READY & AnyMiss & LineDirty);
|
||||
assign SelFlush = (CurrState == STATE_READY & FlushCache) |
|
||||
(CurrState == STATE_FLUSH) |
|
||||
(CurrState == STATE_FLUSH_WRITEBACK);
|
||||
@ -203,17 +194,16 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
|
||||
// Bus interface controls
|
||||
assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | // exclusion-tag: icache CacheBusRCauses
|
||||
(CurrState == STATE_FETCH & ~CacheBusAck) |
|
||||
(CurrState == STATE_WRITEBACK & CacheBusAck & ~CMOp[3]);
|
||||
(CurrState == STATE_WRITEBACK & CacheBusAck & ~(|CMOp));
|
||||
assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | // exclusion-tag: icache CacheBusW
|
||||
(CurrState == STATE_WRITEBACK & ~CacheBusAck) |
|
||||
(CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck) |
|
||||
(P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_WRITEBACK & (CMOp[1] | CMOp[2]) & ~CacheBusAck);
|
||||
(P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2]) & ~CacheBusAck);
|
||||
|
||||
assign SelAdr = (CurrState == STATE_READY & (CacheRW[0] | AnyMiss | (|CMOp))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed
|
||||
(CurrState == STATE_FETCH) |
|
||||
(CurrState == STATE_WRITEBACK) |
|
||||
(CurrState == STATE_WRITE_LINE) |
|
||||
(CurrState == STATE_CMO_WRITEBACK) |
|
||||
resetDelay;
|
||||
assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD;
|
||||
assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; // exclusion-tag: dcache CacheEn
|
||||
|
||||
22
src/cache/cacheway.sv
vendored
22
src/cache/cacheway.sv
vendored
@ -33,7 +33,6 @@ module cacheway import cvw::*; #(parameter cvw_t P,
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations)
|
||||
input logic [3:0] CMOp, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
|
||||
input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant
|
||||
input logic [$clog2(NUMLINES)-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
|
||||
input logic [PA_BITS-1:0] PAdr, // Physical address
|
||||
@ -41,10 +40,8 @@ module cacheway import cvw::*; #(parameter cvw_t P,
|
||||
input logic SetValid, // Set the valid bit in the selected way and set
|
||||
input logic ClearValid, // Clear the valid bit in the selected way and set
|
||||
input logic SetDirty, // Set the dirty bit in the selected way and set
|
||||
input logic CMOZeroHit, // Write zeros to all bytes of a cache line
|
||||
input logic SelWay, // Controls which way to select a way data and tag, 00 = hitway, 10 = victimway, 11 = flushway
|
||||
input logic ClearDirty, // Clear the dirty bit in the selected way and set
|
||||
input logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback
|
||||
input logic SelCMOWriteback,// Overrides cached tag check to select a specific way and set for writeback for both data and tag
|
||||
input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
|
||||
input logic VictimWay, // LRU selected this way as victim to evict
|
||||
input logic FlushWay, // This way is selected for flush and possible writeback if dirty
|
||||
@ -78,32 +75,19 @@ module cacheway import cvw::*; #(parameter cvw_t P,
|
||||
logic ClearDirtyWay;
|
||||
logic SelNonHit;
|
||||
logic SelData;
|
||||
logic SelNotHit2;
|
||||
|
||||
if (P.ZICBOZ_SUPPORTED) begin : cbologic
|
||||
assign SelNotHit2 = SetValid & ~CMOZeroHit;
|
||||
//assign SelNotHit2 = SetValid;
|
||||
|
||||
end else begin : cbologic
|
||||
assign SelNotHit2 = SetValid;
|
||||
end
|
||||
|
||||
if (!READ_ONLY_CACHE) begin:flushlogic
|
||||
logic FlushWayEn;
|
||||
|
||||
mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
|
||||
|
||||
// FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected.
|
||||
// coverage off -item e 1 -fecexprrow 3
|
||||
// nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases.
|
||||
assign FlushWayEn = FlushWay & SelFlush;
|
||||
// *** RT: This is slopy. I should refactor to have the fsm issue two types of writeback commands
|
||||
assign SelNonHit = FlushWayEn | SelNotHit2 | SelWriteback; // *** this is not correct
|
||||
|
||||
//assign SelNonHit = FlushWayEn | SelNotHit2 | SelWriteback;
|
||||
assign SelNonHit = FlushWayEn | SelWay;
|
||||
end else begin:flushlogic // no flush operation for read-only caches.
|
||||
assign SelTag = VictimWay;
|
||||
assign SelNonHit = SelNotHit2;
|
||||
assign SelNonHit = SelWay;
|
||||
end
|
||||
|
||||
mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData);
|
||||
|
||||
@ -52,7 +52,7 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)(
|
||||
// AHB-Lite external signals
|
||||
output logic HCLK, HRESETn,
|
||||
input logic HREADY, // AHB peripheral ready
|
||||
input logic HRESP, // AHB peripheral response. 0: OK 1: Error
|
||||
input logic HRESP, // AHB peripheral response. 0: OK 1: Error. Presently ignored.
|
||||
output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration
|
||||
output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration
|
||||
output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration
|
||||
|
||||
@ -41,7 +41,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision
|
||||
input logic [6:0] OpD, // bits 6:0 of instruction
|
||||
input logic [4:0] Rs2D, // bits 24:20 of instruction
|
||||
input logic [2:0] Funct3D, Funct3E, // bits 14:12 of instruction - may contain rounding mode
|
||||
input logic [2:0] Funct3D, // bits 14:12 of instruction - may contain rounding mode
|
||||
// input mux selections
|
||||
output logic XEnD, YEnD, ZEnD, // enable inputs
|
||||
output logic XEnE, YEnE, ZEnE, // enable inputs
|
||||
|
||||
@ -30,8 +30,7 @@ module fdivsqrtexpcalc import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [P.FMTBITS-1:0] Fmt,
|
||||
input logic [P.NE-1:0] Xe, Ye, // input exponents
|
||||
input logic Sqrt,
|
||||
input logic XZero,
|
||||
input logic [P.DIVBLEN-1:0] ell, m, // number of leading 0s in Xe and Ye
|
||||
input logic [P.DIVBLEN-1:0] ell, m, // number of leading 0s in Xe and Ye
|
||||
output logic [P.NE+1:0] Ue // result exponent
|
||||
);
|
||||
|
||||
|
||||
@ -210,7 +210,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
|
||||
flopen #(P.DIVb+4) dreg(clk, IFDivStartE, {3'b000, Dnorm}, D);
|
||||
|
||||
// Floating-point exponent
|
||||
fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Ue(UeE));
|
||||
fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .ell, .m(mE), .Ue(UeE));
|
||||
flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM);
|
||||
|
||||
// Number of FSM cycles (to FSM)
|
||||
|
||||
@ -167,7 +167,7 @@ module fpu import cvw::*; #(parameter cvw_t P) (
|
||||
|
||||
// calculate FP control signals
|
||||
fctrl #(P) fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]),
|
||||
.Funct3E, .IntDivE, .InstrD,
|
||||
.IntDivE, .InstrD,
|
||||
.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
|
||||
.reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM,
|
||||
.FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM,
|
||||
|
||||
@ -32,7 +32,6 @@ module hazard import cvw::*; #(parameter cvw_t P) (
|
||||
input logic LSUStallM, IFUStallF,
|
||||
input logic FCvtIntStallD, FPUStallD,
|
||||
input logic DivBusyE, FDivBusyE,
|
||||
input logic EcallFaultM, BreakpointFaultM,
|
||||
input logic wfiM, IntPendingM,
|
||||
// Stall & flush outputs
|
||||
output logic StallF, StallD, StallE, StallM, StallW,
|
||||
|
||||
@ -45,7 +45,6 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
|
||||
logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, PreALUResult; // Intermediate Signals
|
||||
logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux
|
||||
logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux
|
||||
logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux
|
||||
logic Carry, Neg; // Flags: carry out, negative
|
||||
logic LT, LTU; // Less than, Less than unsigned
|
||||
logic Asign, Bsign; // Sign bits of A, B
|
||||
|
||||
@ -103,7 +103,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
|
||||
logic BaseRegWriteD; // Indicates if Base instruction register write instruction
|
||||
logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu
|
||||
logic BaseALUSrcBD; // Base instruction ALU B source select signal
|
||||
logic [2:0] ALUControlD; // Determines ALU operation
|
||||
logic ALUSrcAD, ALUSrcBD; // ALU inputs
|
||||
logic ALUResultSrcD, W64D, MDUD; // ALU result, is RV64 W-type, is multiply/divide instruction
|
||||
logic CSRZeroSrcD; // Ignore setting and clearing zeros to CSR
|
||||
@ -118,7 +117,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
|
||||
logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals
|
||||
logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor
|
||||
logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions
|
||||
logic ALUOpE; // 0 for address generationm 1 for ALU operations
|
||||
logic BranchTakenE; // Branch is taken
|
||||
logic eqE, ltE; // Comparator outputs
|
||||
logic unused;
|
||||
|
||||
@ -33,7 +33,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
||||
// Command from CPU
|
||||
input logic InvalidateICacheM, // Clears all instruction cache valid bits
|
||||
input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
|
||||
input logic InstrValidD, InstrValidE, InstrValidM,
|
||||
input logic InstrValidD, InstrValidE,
|
||||
input logic BranchD, BranchE,
|
||||
input logic JumpD, JumpE,
|
||||
// Bus interface
|
||||
@ -103,7 +103,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
||||
logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
|
||||
logic [P.XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
|
||||
logic [P.XLEN-1:0] PCSpillNextF; // Next PCF after possible + 2 to handle spill
|
||||
logic [P.XLEN-1:0] PCLinkD; // PCF2or4F delayed 1 cycle. This is next PC after a control flow instruction (br or j)
|
||||
logic [P.XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F
|
||||
logic [P.XLEN-1:0] PCD; // Decode stage instruction address
|
||||
logic [P.XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence
|
||||
@ -228,7 +227,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
||||
logic [P.PA_BITS-1:0] ICacheBusAdr;
|
||||
logic ICacheBusAck;
|
||||
logic [1:0] CacheBusRW, BusRW, CacheRWF;
|
||||
logic [1:0] CacheBusRWTemp;
|
||||
|
||||
assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
|
||||
assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
|
||||
@ -246,7 +244,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
||||
.ByteMask('0), .BeatCount('0), .SelBusBeat('0),
|
||||
.CacheWriteData('0),
|
||||
.CacheRW(CacheRWF),
|
||||
.CacheAtomic('0), .FlushCache('0),
|
||||
.FlushCache('0),
|
||||
.NextSet(PCSpillNextF[11:0]),
|
||||
.PAdr(PCPF),
|
||||
.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOp('0));
|
||||
|
||||
@ -40,7 +40,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [1:0] AtomicM, // Atomic memory operation
|
||||
input logic FlushDCacheM, // Flush D cache to next level of memory
|
||||
input logic [3:0] CMOpM, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
|
||||
input logic LSUPrefetchM, // Prefetch
|
||||
input logic LSUPrefetchM, // Prefetch; presently unused
|
||||
output logic CommittedM, // Delay interrupts while memory operation in flight
|
||||
output logic SquashSCW, // Store conditional failed disable write to GPR
|
||||
output logic DCacheMiss, // D cache miss for performance counters
|
||||
@ -291,7 +291,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
||||
logic [1:0] BusRW; // Uncached bus memory access
|
||||
logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush
|
||||
logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11)
|
||||
logic [1:0] CacheAtomicM; // Cache AMO
|
||||
logic FlushDCache; // Suppress d cache flush if there is an ITLB miss.
|
||||
logic CacheStall;
|
||||
logic [1:0] CacheBusRWTemp;
|
||||
@ -299,12 +298,11 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
||||
assign BusRW = ~CacheableM & ~SelDTIM ? LSURWM : '0;
|
||||
assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
|
||||
assign CacheRWM = CacheableM & ~SelDTIM ? LSURWM : '0;
|
||||
assign CacheAtomicM = CacheableM & ~SelDTIM ? LSUAtomicM : '0;
|
||||
assign FlushDCache = FlushDCacheM & ~(SelHPTW);
|
||||
|
||||
cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
|
||||
.NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
|
||||
.clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB), .CacheRW(SelStoreDelay ? 2'b00 : CacheRWM), .CacheAtomic(CacheAtomicM),
|
||||
.clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB), .CacheRW(SelStoreDelay ? 2'b00 : CacheRWM),
|
||||
.FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM),
|
||||
.ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
|
||||
.CacheWriteData(LSUWriteDataSpillM), .SelHPTW,
|
||||
|
||||
@ -38,8 +38,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [P.XLEN-1:0] SrcAM, IEUAdrM, // SrcA and memory address from IEU
|
||||
input logic CSRReadM, CSRWriteM, // read or write CSR
|
||||
input logic TrapM, // trap is occurring
|
||||
input logic mretM, sretM, wfiM, // return or WFI instruction
|
||||
input logic IntPendingM, // at least one interrupt is pending and could occur if enabled
|
||||
input logic mretM, sretM, // return instruction
|
||||
input logic InterruptM, // interrupt is occurring
|
||||
input logic ExceptionM, // interrupt is occurring
|
||||
input logic MTimerInt, // timer interrupt
|
||||
@ -248,7 +247,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
|
||||
csrs #(P) csrs(.clk, .reset,
|
||||
.CSRSWriteM, .STrapM, .CSRAdrM,
|
||||
.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
|
||||
.STATUS_TVM, .MCOUNTEREN_TM(MCOUNTEREN_REGW[1]),
|
||||
.STATUS_TVM,
|
||||
.CSRWriteValM, .PrivilegeModeW,
|
||||
.CSRSReadValM, .STVEC_REGW, .SEPC_REGW,
|
||||
.SCOUNTEREN_REGW,
|
||||
|
||||
@ -60,7 +60,7 @@ module csrm import cvw::*; #(parameter cvw_t P) (
|
||||
|
||||
// Machine CSRs
|
||||
localparam MVENDORID = 12'hF11;
|
||||
localparam MARCHID = 12'hF12;
|
||||
localparam MARCHID = 12'hF12; // github.com/riscv/riscv-isa-manual/blob/main/marchid.md
|
||||
localparam MIMPID = 12'hF13;
|
||||
localparam MHARTID = 12'hF14;
|
||||
localparam MCONFIGPTR = 12'hF15;
|
||||
@ -216,8 +216,8 @@ module csrm import cvw::*; #(parameter cvw_t P) (
|
||||
end
|
||||
else case (CSRAdrM)
|
||||
MISA_ADR: CSRMReadValM = MISA_REGW;
|
||||
MVENDORID: CSRMReadValM = 0;
|
||||
MARCHID: CSRMReadValM = 0;
|
||||
MVENDORID: CSRMReadValM = {{(P.XLEN-32){1'b0}}, 32'h0000_0602}; // OpenHW JEDEC
|
||||
MARCHID: CSRMReadValM = {{(P.XLEN-32){1'b0}}, 32'h24}; // 36 for CV-Wally
|
||||
MIMPID: CSRMReadValM = {{P.XLEN-12{1'b0}}, 12'h100}; // pipelined implementation
|
||||
MHARTID: CSRMReadValM = MHARTID_REGW; // hardwired to 0
|
||||
MCONFIGPTR: CSRMReadValM = 0; // hardwired to 0
|
||||
|
||||
@ -35,7 +35,6 @@ module csrs import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [P.XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW,
|
||||
input logic [4:0] NextCauseM,
|
||||
input logic STATUS_TVM,
|
||||
input logic MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear
|
||||
input logic [P.XLEN-1:0] CSRWriteValM,
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
output logic [P.XLEN-1:0] CSRSReadValM, STVEC_REGW,
|
||||
|
||||
@ -29,7 +29,7 @@
|
||||
|
||||
module privdec import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk, reset,
|
||||
input logic StallM, StallW, FlushW,
|
||||
input logic StallW, FlushW,
|
||||
input logic [31:15] InstrM, // privileged instruction function field
|
||||
input logic PrivilegedM, // is this a privileged instruction (from IEU controller)
|
||||
input logic IllegalIEUFPUInstrM, // Not a legal IEU instruction
|
||||
|
||||
@ -93,7 +93,6 @@ module privileged import cvw::*; #(parameter cvw_t P) (
|
||||
input logic InvalidateICacheM, // fence instruction
|
||||
output logic BigEndianM, // Use big endian in current privilege mode
|
||||
// Fault outputs
|
||||
output logic BreakpointFaultM, EcallFaultM, // breakpoint and Ecall traps should retire
|
||||
output logic wfiM, IntPendingM // Stall in Memory stage for WFI until interrupt pending or timeout
|
||||
);
|
||||
|
||||
@ -114,6 +113,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
|
||||
logic InterruptM; // interrupt occuring
|
||||
logic ExceptionM; // Memory stage instruction caused a fault
|
||||
logic HPTWInstrAccessFaultM; // Hardware page table access fault while fetching instruction PTE
|
||||
logic BreakpointFaultM, EcallFaultM; // breakpoint and Ecall traps should retire
|
||||
|
||||
logic wfiW;
|
||||
|
||||
@ -122,7 +122,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
|
||||
.STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
|
||||
|
||||
// decode privileged instructions
|
||||
privdec #(P) pmd(.clk, .reset, .StallM, .StallW, .FlushW, .InstrM(InstrM[31:15]),
|
||||
privdec #(P) pmd(.clk, .reset, .StallW, .FlushW, .InstrM(InstrM[31:15]),
|
||||
.PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM,
|
||||
.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM,
|
||||
.EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .wfiW, .sfencevmaM);
|
||||
@ -130,7 +130,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
|
||||
// Control and Status Registers
|
||||
csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
|
||||
.InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF,
|
||||
.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
|
||||
.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
|
||||
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
|
||||
.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
|
||||
.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,
|
||||
|
||||
@ -68,11 +68,10 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
||||
// Watermark signals - TransmitReadMark = ip[0], ReceiveWriteMark = ip[1]
|
||||
logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark;
|
||||
logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty;
|
||||
logic TransmitFIFOReadIncrement;
|
||||
logic TransmitFIFOWriteIncrement;
|
||||
logic ReceiveFIFOReadIncrement;
|
||||
logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty;
|
||||
logic [7:0] TransmitFIFOReadData, ReceiveFIFOWriteData;
|
||||
logic [7:0] TransmitFIFOReadData;
|
||||
logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel;
|
||||
logic [7:0] ReceiveShiftRegEndian; // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
|
||||
|
||||
@ -92,7 +91,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
||||
|
||||
// Frame counting signals
|
||||
logic [3:0] FrameCount; // Counter for number of frames in transmission
|
||||
logic [3:0] ReceivePenultimateFrameCount; // Counter
|
||||
logic ReceivePenultimateFrame; // High when penultimate frame in transmission has been reached
|
||||
|
||||
// State fsm signals
|
||||
|
||||
@ -158,7 +158,6 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
logic DCacheAccess;
|
||||
logic ICacheMiss;
|
||||
logic ICacheAccess;
|
||||
logic BreakpointFaultM, EcallFaultM;
|
||||
logic InstrUpdateDAF;
|
||||
logic BigEndianM;
|
||||
logic FCvtIntE;
|
||||
@ -170,7 +169,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
// instruction fetch unit: PC, branch prediction, instruction cache
|
||||
ifu #(P) ifu(.clk, .reset,
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.InstrValidM, .InstrValidE, .InstrValidD,
|
||||
.InstrValidE, .InstrValidD,
|
||||
.BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF,
|
||||
// Fetch
|
||||
.HRDATA, .PCSpillF, .IFUHADDR, .PC2NextF,
|
||||
@ -270,7 +269,6 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
.LSUStallM, .IFUStallF,
|
||||
.FCvtIntStallD, .FPUStallD,
|
||||
.DivBusyE, .FDivBusyE,
|
||||
.EcallFaultM, .BreakpointFaultM,
|
||||
.wfiM, .IntPendingM,
|
||||
// Stall & flush outputs
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW,
|
||||
@ -298,7 +296,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
.PrivilegeModeW, .SATP_REGW,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
|
||||
.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .wfiM, .IntPendingM, .BigEndianM);
|
||||
end else begin
|
||||
assign CSRReadValW = 0;
|
||||
assign UnalignedPCNextF = PC2NextF;
|
||||
|
||||
@ -67,6 +67,7 @@ def synthsintocsv():
|
||||
|
||||
for oneSynth in allSynths:
|
||||
module, width, risc, tech, freq = specReg.findall(oneSynth)[1:6]
|
||||
tech = tech[:-2]
|
||||
metrics = []
|
||||
for phrase in [["Path Slack", "qor"], ["Design Area", "qor"], ["100", "power"]]:
|
||||
bashCommand = 'grep "{}" ' + oneSynth[2:] + "/reports/*{}*"
|
||||
|
||||
@ -23,6 +23,7 @@
|
||||
`define NUM_REGS 32
|
||||
`define NUM_CSRS 4096
|
||||
|
||||
`define STD_LOG 1
|
||||
`define PRINT_PC_INSTR 0
|
||||
`define PRINT_MOST 0
|
||||
`define PRINT_ALL 0
|
||||
@ -495,8 +496,38 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
||||
|
||||
integer index2;
|
||||
|
||||
string instrWName;
|
||||
int file;
|
||||
string LogFile;
|
||||
if(`STD_LOG) begin
|
||||
instrNameDecTB NameDecoder(rvvi.insn[0][0], instrWName);
|
||||
initial begin
|
||||
LogFile = "InstrTrace.log";
|
||||
file = $fopen(LogFile, "w");
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if(rvvi.valid[0][0]) begin
|
||||
if(`STD_LOG) begin
|
||||
$fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
|
||||
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
|
||||
if(rvvi.x_wb[0][0][index2]) begin
|
||||
$fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]);
|
||||
end
|
||||
end
|
||||
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
|
||||
if(rvvi.f_wb[0][0][index2]) begin
|
||||
$fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]);
|
||||
end
|
||||
end
|
||||
for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
|
||||
if(rvvi.csr_wb[0][0][index2]) begin
|
||||
$fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]);
|
||||
end
|
||||
end
|
||||
$fwrite(file, "\n");
|
||||
end
|
||||
if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
|
||||
$display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]);
|
||||
else if(`PRINT_MOST & !`PRINT_ALL)
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
hart_ids: [0]
|
||||
hart0:
|
||||
ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
|
||||
ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs
|
||||
physical_addr_sz: 32
|
||||
User_Spec_Version: '2.3'
|
||||
supported_xlen: [32]
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
hart_ids: [0]
|
||||
hart0:
|
||||
ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
|
||||
ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs
|
||||
physical_addr_sz: 56
|
||||
User_Spec_Version: '2.3'
|
||||
supported_xlen: [64]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user