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Merge pull request #490 from davidharrishmc/dev

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Synthesis running for textbook, preload IROM to avoid it being optimized out, updated M tests in risk-arch-test
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Rose Thompson 2023-11-19 20:42:29 -08:00 committed by GitHub
commit 17e91f31f6
8 changed files with 27 additions and 10 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit 9f9bdd62d3e37fcd8ad1b1a39d71694ccf1d74f3
Subproject commit eb0a3892215ad2384702db02da1551a59701ec67

7
benchmarks/embench/embench_arch_sweep.py
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@ -10,7 +10,8 @@ from datetime import datetime
import re
import collections
archs = ["rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr", "rv32imafdc_zba_zbb_zbc_zbs_zicsr"]
#archs = ["rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr", "rv32imafdc_zba_zbb_zbc_zbs_zicsr"]
archs = ["rv32imafdc_zba_zbb_zbc_zbs_zicsr", "rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr"]
def calcgeomean(d, arch):
progs = ["aha-mont64", "crc32", "cubic", "edn", "huffbench", "matmult-int", "minver", "nbody", "nettle-aes", "nettle-sha256", "nsichneu", "picojpeg", "qrduino", "sglib-combined", "slre", "st", "statemate", "ud", "wikisort"]
@ -81,6 +82,6 @@ def run_arch_sweep():
os.system("mv -f wally"+res+".json "+dir+"/wally"+res+"_"+arch+".json")
return dir
#directory = run_arch_sweep()
directory = "run_20231116_071322"
directory = run_arch_sweep()
#directory = "run_20231117_082325"
tabulate_arch_sweep(directory)

2
config/rv32gc/config.vh
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@ -169,7 +169,7 @@ localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture
localparam RADIX = 32'd4;
localparam DIVCOPIES = 32'd4;
localparam DIVCOPIES = 32'd2;
// bit manipulation
localparam ZBA_SUPPORTED = 1;

2
src/generic/mem/rom1p1r.sv
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@ -47,7 +47,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
initial begin
if (PRELOAD_ENABLED) begin
$readmemh("../../../fpga/src/boot.mem", ROM, 0);
$readmemh("$WALLY/fpga/src/boot.mem", ROM, 0);
end
end

4
src/ifu/irom.sv
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@ -39,7 +39,9 @@ module irom import cvw::*; #(parameter cvw_t P) (
logic [31:0] RawIROMInstrF;
logic [2:1] AdrD;
rom1p1r #(ADDR_WDITH, P.XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
// preload IROM with the FPGA bootloader by default so that it syntehsizes to something, avoiding having the IEU optimized away because instructions are all 0
// the testbench replaces these dummy contents with the actual program of interest during simulation
rom1p1r #(ADDR_WDITH, P.XLEN, 1) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
if (P.XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
else begin
// IROM is aligned to XLEN words, but instructions are 32 bits. Select between the two

4
synthDC/Makefile
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@ -94,10 +94,10 @@ endif
ifneq ($(MOD), orig)
# PMP 0
sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES = 0;/' $(CONFIGDIR)/config.vh
sed -i 's/PMP_ENTRIES.*\(64\|16\)/PMP_ENTRIES = 0;/' $(CONFIGDIR)/config.vh
ifneq ($(MOD), PMP0)
# no priv
sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED = 0;/' $(CONFIGDIR)/config.vh
sed -i 's/ZICSR_SUPPORTED.*1/ZICSR_SUPPORTED = 0;/' $(CONFIGDIR)/config.vh
ifneq ($(MOD), noPriv)
# turn off FPU
sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/config.vh

2
synthDC/extractSummary.py
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@ -252,7 +252,7 @@ if __name__ == '__main__':
TechSpec = namedtuple("TechSpec", "color shape targfreq fo4 add32area add32lpower add32denergy")
techdict = {}
techdict['sky130'] = TechSpec('green', 'o', args.sky130freq, 99.5e-3, 1440.600027, 714.057, 0.658023)
techdict['sky130'] = TechSpec('green', 'o', args.sky130freq, 99.5e-3, 2581, 18, 0.685)
techdict['sky90'] = TechSpec('gray', 'o', args.sky90freq, 43.2e-3, 1440.600027, 714.057, 0.658023)
techdict['tsmc28psyn'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533)

14
synthDC/wallySynthAll.sh Executable file
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@ -0,0 +1,14 @@
# Run all Wally synthesis experiments from chapter 8
# However, trying to run the freqsweeps at the same time maxes out licenses and some runs fail
#./wallySynth.py --freqsweep 330 --tech sky130
#./wallySynth.py --freqsweep 870 --tech sky90
#./wallySynth.py --freqsweep 2800 --tech tsmc28psyn --usesram
./wallySynth.py --configsweep --tech sky130 --targetfreq 330
./wallySynth.py --configsweep --tech sky90 --targetfreq 870
./wallySynth.py --configsweep --tech tsmc28psyn --targetfreq 2800 --usesram
./wallySynth.py --featuresweep --tech sky130 --targetfreq 330
./wallySynth.py --featuresweep --tech sky90 --targetfreq 870
./wallySynth.py --featuresweep --tech tsmc28psyn --targetfreq 2800 --usesram
# Extract summary data (run this by hand after all experiments finish)
#./extractSummary.py --sky130freq 330 --sky90freq 870 --tsmcfreq 2800