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Author SHA1 Message Date
Ross Thompson
a8fbbb0631 Fixed up the bit widths on the page table walker for rv32. 2021-07-02 15:45:05 -05:00
Ross Thompson
46831035fb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-02 13:56:49 -05:00
Katherine Parry
4a6abe0f50 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-02 12:56:53 -04:00
Katherine Parry
72406b8a88 FPU update - missing files 2021-07-02 12:53:05 -04:00
Ross Thompson
549b7b2a62 Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
David Harris
1ce98cc100 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-02 12:52:20 -04:00
Katherine Parry
3f61e313d2 FPU update 2021-07-02 12:40:58 -04:00
David Harris
cd6cabac2f Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:05:25 -04:00
David Harris
648c09e5ef Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:04:13 -04:00
Ross Thompson
2616f41f91 reverted change to the imperas tests order. Accidently commited change which placed the virtual memory tests first. 2021-07-01 18:04:43 -05:00
Ross Thompson
386193de00 added page table walker fault exit for icache. 2021-07-01 17:59:55 -05:00
Ross Thompson
3dae02818c OMG. It's working! 2021-07-01 17:37:53 -05:00
Ross Thompson
9139cd2954 Fixed tab space issue. 2021-07-01 17:17:53 -05:00
Ross Thompson
c3eaa3169e Fixed the wrong virtual address write into the dtlb. 2021-07-01 16:55:16 -05:00
Teo Ene
c7c4916efd Correct physical implementation flow path 2021-07-01 16:37:49 -05:00
Teo Ene
1d5d7a7840 Flow updated for 90nm 2021-07-01 13:32:42 -05:00
Ross Thompson
9d9415ea67 Got some stores working in virtual memory. 2021-07-01 12:49:09 -05:00
Ross Thompson
be6468c6d9 Icache ITLB interlock fix. 2021-06-30 19:24:59 -05:00
Ross Thompson
4530e43df6 The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay. 2021-06-30 17:02:36 -05:00
Ross Thompson
07a0b66fdf Major rewrite of ptw to remove combo loop. 2021-06-30 16:25:03 -05:00
Ross Thompson
b31e0afc2a The icache now correctly interlocks with the PTW on TLB miss. 2021-06-30 11:24:26 -05:00
Ross Thompson
2598f08782 Page table walker now walks the table. 
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
 2021-06-29 22:33:57 -05:00
Katherine Parry
6216bd7172 FPU control signals changed and FMA works 2021-06-28 18:53:58 -04:00
Ross Thompson
ae6140bd94 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
bbracker
a7f810e2c4 trying out Noah and Kaveh's proposed hack for which CSRs to update for QEMU MMU bug 2021-06-26 08:30:58 -04:00
bbracker
61495f74ac Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-26 08:29:37 -04:00
bbracker
aa8da43743 temporarily disable PMP checking for EBU accesses. 2021-06-26 07:19:51 -04:00
bbracker
59b2a49854 split intermediate GDB output file into smaller files for better debug experience 2021-06-26 07:18:26 -04:00
Ross Thompson
8dfbf60b67 AMO and LR/SC instructions now working correctly. 
Page table walking is not working.
 2021-06-25 15:42:07 -05:00
Abe
b6426c5fbf Updated timing functions to read from MTIME register, TICKS_PER_SEC set to 10000 so timer reads millisecs 2021-06-25 16:42:03 -04:00
Abe
ff8b421e6c Fixed Coremark Score output printing. Also made it so that the loop that sets the iteration count increments iterations by 1 instead by increasing it by a factor of 10 each time (which was overkill for the timing that's needed to exit the loop) 2021-06-25 16:27:23 -04:00
Ross Thompson
a4266c0136 Some progress. Had to change how the page table walker got it's ready. 2021-06-25 15:07:41 -05:00
Ross Thompson
9fd1761fd6 Working through a combo loop. 2021-06-25 14:49:27 -05:00
Ross Thompson
17636b3293 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
bbracker
9927f771cc linux testbench now ignores HWRITE glitches caused by flush glitches 2021-06-25 09:28:52 -04:00
bbracker
2694a7a43f made testbench-linux's PCDwrong be FlushD 2021-06-25 08:15:19 -04:00
bbracker
4e09793a9a ah merge; I checked and this does pass all of regression except lints 2021-06-25 07:37:06 -04:00
bbracker
aac9b46a1f changed SC M-to-E fowarding to W-to-E forwarding to improve critical path 2021-06-25 07:18:38 -04:00
Kip Macsai-Goren
1485d29dde Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR. 2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
389b9a510e Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations. 2021-06-24 19:59:29 -04:00
Katherine Parry
bc8d660bc5 FPU forwarding reworked pt.1 2021-06-24 18:39:18 -04:00
bbracker
ced5039776 Revert "fixed forwarding" 
This reverts commit 0f4a4a6ade.
 2021-06-24 17:39:37 -04:00
Ross Thompson
d8183e59e4 Works until pma checker breaks the simulation by reading HADDR rather than data physical address. 2021-06-24 14:42:59 -05:00
Ross Thompson
732551d6be Fixed combo loop in between the page table walker and i/dtlb. 2021-06-24 13:47:10 -05:00
Ross Thompson
0377d3b2c9 Progress. 2021-06-24 13:05:22 -05:00
bbracker
0f4a4a6ade fixed forwarding 2021-06-24 11:20:21 -04:00
bbracker
3ae4cd951a make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses 2021-06-24 08:35:00 -04:00
bbracker
3d6b422e34 regression can overcome the fact that buildroots UART prints stuff 2021-06-24 02:00:01 -04:00
bbracker
409a73604c whoops meant to remove notifications from busybear, not buildroot 2021-06-24 01:54:46 -04:00
bbracker
55cf205222 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-24 01:42:41 -04:00