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Configurable RISC-V Processor
1,096 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
2598f08782
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Ross Thompson 2598f08782 Page table walker now walks the table. 
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
riscv-coremark Commit message 2021-06-17 14:49:13 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined Page table walker now walks the table. 2021-06-29 22:33:57 -05:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore added slack notifier for long sims 2021-06-22 08:31:41 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor