Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
1,102 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
6216bd7172
Go to file
Katherine Parry 6216bd7172 FPU control signals changed and FMA works
2021-06-28 18:53:58 -04:00
riscv-coremark Updated timing functions to read from MTIME register, TICKS_PER_SEC set to 10000 so timer reads millisecs 2021-06-25 16:42:03 -04:00
sky130
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined FPU control signals changed and FMA works 2021-06-28 18:53:58 -04:00
.gitattributes
.gitignore split intermediate GDB output file into smaller files for better debug experience 2021-06-26 07:18:26 -04:00
.gitmodules
LICENSE
README.md

README.md

riscv-wally

Configurable RISC-V Processor