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Configurable RISC-V Processor
1,106 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
3f61e313d2
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Katherine Parry 3f61e313d2 FPU update
2021-07-02 12:40:58 -04:00
riscv-coremark Updated timing functions to read from MTIME register, TICKS_PER_SEC set to 10000 so timer reads millisecs 2021-06-25 16:42:03 -04:00
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined FPU update 2021-07-02 12:40:58 -04:00
.gitattributes
.gitignore split intermediate GDB output file into smaller files for better debug experience 2021-06-26 07:18:26 -04:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
LICENSE
README.md

README.md

riscv-wally

Configurable RISC-V Processor