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Author	SHA1	Message	Date
naichewa	4651b807ed	added test cases	2023-11-02 15:43:08 -07:00
naichewa	29e42b21df	added test cases	2023-11-02 15:42:28 -07:00
Rose Thompson	0a4ed5515b	Merge branch 'main' into Zicclsm	2023-11-02 12:55:51 -05:00
Rose Thompson	7222aaa196	Enabled Zicclsm in rv64gc.	2023-11-02 12:47:40 -05:00
Rose Thompson	455b78362c	Merge pull request #449 from davidharrishmc/dev ... Synthesis cleanup	2023-11-02 12:26:55 -05:00
Rose Thompson	afa1d85e3b	Doesn't yet fully work. ... Thomas is going to finish debugging while I'm on the RISCV summit next week.	2023-11-02 12:07:42 -05:00
David Harris	bf65ce0f9f	Removed .gitattributes	2023-11-01 17:50:44 -07:00
Rose Thompson	7ba891f607	Progress. I think the remaining bugs are in the regression test's signature.	2023-11-01 17:51:48 -05:00
Rose Thompson	13333d3e82	Finally the d$ spill works. At least until the next bug. Definitely needs a lot of cleanup.	2023-11-01 14:25:18 -05:00
naichewa	a08356fdaa	correct exclusion tags and reset testbench	2023-11-01 10:34:39 -07:00
naichewa	e3d8162279	harris code review 3	2023-11-01 10:14:15 -07:00
David Harris	31d9ec08cb	Improved comments about memory read paths	2023-11-01 07:00:17 -07:00
naichewa	9aa8a7af3e	comments, more test cases	2023-11-01 01:26:34 -07:00
Rose Thompson	5660eff57d	Working through issues with the psill logic.	2023-10-31 18:50:13 -05:00
Rose Thompson	4984b3935f	Progress	2023-10-31 14:50:33 -05:00
naichewa	fefb5adb8f	code review harris	2023-10-31 12:27:41 -07:00
Rose Thompson	5ca428d6a8	Fixed bugs in misaligned test.	2023-10-31 12:49:35 -05:00
Rose Thompson	c061440141	First stab at the misaligned test.	2023-10-31 12:30:10 -05:00
David Harris	dccd7bf5ee	Fixes to config extraction	2023-10-31 06:27:55 -07:00
David Harris	5112bfed19	130 nm synthesis script improvements	2023-10-30 20:57:35 -07:00
David Harris	680fb3f30b	Conditionally instantiate hardware in ifu	2023-10-30 20:55:00 -07:00
David Harris	afabc52b61	Gated InstrOrigM and PCMReg when not needed	2023-10-30 20:05:37 -07:00
David Harris	2d17a991d8	rom1p1r code cleanup	2023-10-30 19:47:49 -07:00
David Harris	3f7c67882f	rom1p1r code cleanup	2023-10-30 19:46:38 -07:00
David Harris	90a178e31e	Made 2-bit AdrReg conditional on being needed	2023-10-30 19:13:43 -07:00
naichewa	7dd3f24d6c	Merge branch 'main' into spi	2023-10-30 17:01:41 -07:00
naichewa	2330f4ee63	hardware interlock	2023-10-30 17:00:20 -07:00
Rose Thompson	2241976d29	Updated mmu to not generate trap on cacheable misaligned access when supported. ... Updated tests with David's help.	2023-10-30 18:26:11 -05:00
Rose Thompson	f13b67b869	Preemptively fixed the bytemask bug before testing.	2023-10-30 15:47:46 -05:00
Rose Thompson	b5763e11e8	rv32gc now also works with the alignment module. Still not tested with misligned access.	2023-10-30 15:30:09 -05:00
Rose Thompson	9cd2e47783	Aligner is integrated and enabled in rv64gc and passes the regression test; however, there are no new tests.	2023-10-30 14:54:58 -05:00
Rose Thompson	569e3dc906	Finally lints cleanly.	2023-10-30 14:00:49 -05:00
Rose Thompson	89de8cd23c	Merge pull request #445 from davidharrishmc/dev ... Fix issue 444; no delegating misaligned instructions if they can't happen	2023-10-30 12:25:42 -05:00
David Harris	f6a7f707bd	Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.	2023-10-30 09:56:17 -07:00
David Harris	27b8ebb9bd	Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported.	2023-10-30 07:06:34 -07:00
Rose Thompson	dce3c85105	Progress.	2023-10-27 16:31:22 -05:00
Rose Thompson	747f453bb5	Passes lint with some exceptions. Still need to add misaligned store support.	2023-10-27 14:41:42 -05:00
Rose Thompson	36ca64c567	At least have the aligner integrated, but not tested.	2023-10-27 13:55:16 -05:00
Rose Thompson	657409aec5	Addec ZICCLSM to config files and started on lsu instance.	2023-10-27 13:07:23 -05:00
Rose Thompson	6041bf20b3	The misaligned load alignment lints.	2023-10-27 11:41:49 -05:00
Rose Thompson	834c0df697	Added file.	2023-10-27 09:49:44 -05:00
Rose Thompson	449abef823	Progress on misaligned load/stores.	2023-10-27 09:35:44 -05:00
Rose Thompson	50a1d731c0	Merge pull request #443 from davidharrishmc/dev ... Wrapper synthesis fix.	2023-10-27 09:25:06 -05:00
David Harris	09c4aaa5d9	Fixed reporting of timing on modules with wrappers	2023-10-26 20:14:14 -07:00
David Harris	734bf021d7	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-10-26 19:02:05 -07:00
David Harris	8cf81a2bb8	Merge pull request #441 from ross144/main ... Fixed issues #200	2023-10-26 10:26:58 -07:00
Rose Thompson	06b5a92eff	Updated comments about Interrupt and wfi.	2023-10-26 12:24:36 -05:00
Rose Thompson	4cd0584a11	Forgot to include this file in the last commit.	2023-10-26 12:20:42 -05:00
Rose Thompson	14f8b4849f	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-10-26 12:15:22 -05:00
Rose Thompson	12763b7297	begin implemenation of Zicclsm.	2023-10-26 11:51:20 -05:00