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Author	SHA1	Message	Date
David Harris	a77bea9954	Merge pull request #472 from ross144/main ... Merge Zicclsm into main branch and removes the FPGA config. FPGA makefile now automatically creates the config when building	2023-11-14 08:34:06 -08:00
David Harris	b67b1f5719	Merge pull request #471 from stineje/main ... Fix multitude of issues with plotPPA as well as issue related to Popen issuing too many synthesis	2023-11-14 05:51:20 -08:00
James E. Stine	9dce08a743	minor typo on ppaSynth and ppaAnalyze	2023-11-14 02:41:44 -06:00
James E. Stine	c722e2c59d	fix plotPPA and other excruciatingly painful problems related to using allWidths and causing empty arrays to be used. This generates the normalized/unnormalized plots	2023-11-14 01:06:14 -06:00
James E. Stine	6374d1a200	Modify ppaSynth.py to be able to not issue excess number of operations with Pool command. This is due to the original command using the Popen command, whereas, using the subprocess.call command solves this issue. The relieves the python script from issuing a ton of synthesis commands and using up all the licenses	2023-11-14 01:04:37 -06:00
Rose Thompson	d4bc9da085	Fixed another bug in the updated script changes.	2023-11-13 18:12:02 -06:00
Rose Thompson	919b7cccf1	Merge branch 'main' of github.com:ross144/cvw	2023-11-13 18:10:35 -06:00
Rose Thompson	f8b65f50b0	Fixed bugs in the updated fpga synthe script.	2023-11-13 18:10:22 -06:00
Rose Thompson	05eb5460b4	Removed fpga config. No longer needed.	2023-11-13 17:50:29 -06:00
Rose Thompson	d5f0c15b90	Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.	2023-11-13 17:48:28 -06:00
Rose Thompson	95fc5f4a1c	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
Rose Thompson	6b7ff50a84	Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.	2023-11-13 16:44:02 -06:00
Rose Thompson	a6995af91c	Fixed bug in uncore updates which broke SDC.	2023-11-13 16:15:23 -06:00
Rose Thompson	707b0c557c	Cleanup and optimization of Zicclsm.	2023-11-13 14:28:22 -06:00
Rose Thompson	da59cb71a9	Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.	2023-11-13 14:12:27 -06:00
Rose Thompson	540d8d930d	Cleanup. ... Linux makefile wally tracer. probably reduce some complexity here.	2023-11-13 14:04:43 -06:00
Rose Thompson	1f7d91e8e0	Merge branch 'Zicclsm'	2023-11-13 13:53:42 -06:00
Rose Thompson	55bcc4dbc1	Updates to linux config files for sdc.	2023-11-13 13:53:23 -06:00
David Harris	18dddb85b5	Merge pull request #470 from stineje/main ... Remove ppa_ prefix and modify ppaAnalyze.py to handle correct vector	2023-11-13 11:25:38 -08:00
Rose Thompson	13908ac41c	Updated buildroot to use kernel 6.6 and added dedicated qemu emulation script.	2023-11-13 12:36:32 -06:00
Rose Thompson	cc7a0b211a	Cleanup.	2023-11-13 12:35:11 -06:00
James E. Stine	74056246d4	Remove ppa_ prefix and modify ppaAnalyze.py to handle correct vector	2023-11-13 10:02:10 -06:00
David Harris	62ab604113	Merge pull request #469 from stineje/main ... update ppaAnalyze to analyze correctionly freqSweep	2023-11-13 05:33:37 -08:00
James E. Stine	46bfdf5df9	update ppaAnalyze to analyze correctionly freqSweep	2023-11-13 02:39:25 -06:00
Rose Thompson	8235f66af8	Merge pull request #468 from davidharrishmc/dev ... Divider optimization	2023-11-12 20:05:44 -08:00
David Harris	571c7d3be4	Divider cleanup	2023-11-12 19:41:12 -08:00
David Harris	f437336540	Explained sqrt preshifting	2023-11-12 10:05:54 -08:00
David Harris	7c50b2c571	Renamed qsel to uslc and simplified radix2 uslc	2023-11-12 06:36:57 -08:00
David Harris	002034845a	fdivsqrt comment improvements	2023-11-12 06:15:47 -08:00
Rose Thompson	4c2a9c7bab	Merge pull request #467 from davidharrishmc/main ... Sanity in FDIVSQRT bit counts	2023-11-11 16:37:25 -08:00
David Harris	6ac83c776e	Cleaned up number of bits in fdivsqrt	2023-11-11 15:50:06 -08:00
David Harris	2bf5143163	Bug fixes related to size of fpdivsqrt bit count and number of cycles	2023-11-11 05:58:53 -08:00
David Harris	448ced00c5	Fixed testbench-fp to reflect signal name changes	2023-11-11 04:05:34 -08:00
Rose Thompson	0d6fb879aa	Merge pull request #466 from stineje/main ... Add pap runs for sweep	2023-11-10 22:25:55 -08:00
Rose Thompson	3af8e1ff50	Merge pull request #465 from davidharrishmc/dev ... fdivsqrt cleanup	2023-11-10 22:25:09 -08:00
James E. Stine	7b79d8edeb	Update scripts/synth.tcl to add with parameter for width and also checks wrapper to see if running CONFIG=rv32e to run without WIDTH	2023-11-10 21:10:35 -06:00
James E. Stine	65e536e401	Update ppa/ppaSynth.py for sky130 and better sweep parameterization	2023-11-10 21:07:36 -06:00
James E. Stine	e1c935bd9b	Add bestSynths.csv that are the initial values. If this is re-run after ppaAnalysis.py is run, more refinement can be made	2023-11-10 21:06:24 -06:00
James E. Stine	91d7790251	update README for ppaSynth.py	2023-11-10 21:05:42 -06:00
David Harris	d5ba8fc5e6	fdivsqrt parameter cleanup	2023-11-10 18:33:08 -08:00
David Harris	3cae2385ab	Simplified out LOGRK parameter	2023-11-10 18:19:41 -08:00
David Harris	7d0d9dcebe	divider cleanup	2023-11-10 18:01:13 -08:00
David Harris	03864642a7	fdivsqrt cleanup	2023-11-10 16:42:32 -08:00
David Harris	c5b12b7331	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-10 16:40:54 -08:00
Rose Thompson	c8cca8dfb8	Simplification.	2023-11-10 18:39:36 -06:00
Rose Thompson	9dfe421c55	Yay! Zicclsm passes my regression test now.	2023-11-10 18:28:51 -06:00
Rose Thompson	c0e02ae190	Found another bug in the RTL's Zicclsm alignment.	2023-11-10 18:26:55 -06:00
Rose Thompson	02ab9fe99c	Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.	2023-11-10 17:58:42 -06:00
Rose Thompson	bd866e1025	Fixed some more bugs in the Zicclsm signature.	2023-11-10 17:36:10 -06:00
Rose Thompson	efecb0c346	Fixed bug in the Zicclsm test.	2023-11-10 17:34:23 -06:00