Kip Macsai-Goren
|
d668c563f4
|
Merge remote-tracking branch 'upstream/main' into main
|
2023-02-21 14:48:41 -08:00 |
|
David Harris
|
99a1683f8e
|
Debug test case updates
|
2023-02-21 09:33:36 -08:00 |
|
Kip Macsai-Goren
|
65a5b86dd8
|
Merge remote-tracking branch 'upstream/main' into main
|
2023-02-19 16:37:18 -08:00 |
|
David Harris
|
f0c0111ab0
|
Renamed section 12.3 to 8.3 in MMU test definitions
|
2023-02-19 05:46:46 -08:00 |
|
Kip Macsai-Goren
|
9c3aa55349
|
merge upstream synth changes
|
2023-02-18 14:35:19 -08:00 |
|
Kip Macsai-Goren
|
ea38e05773
|
fixed makefile for 32 bit arch tests, restored original make for all others
|
2023-02-17 09:57:56 -08:00 |
|
Kip Macsai-Goren
|
7344f3ef30
|
Modified arch64 tests to remove floating point and double tests from hanging make
|
2023-02-17 09:51:55 -08:00 |
|
David Harris
|
2b80004db4
|
Debug test case update
|
2023-02-15 06:42:38 -08:00 |
|
Kevin Kim
|
4fed8d9196
|
added critical rsync command to python script and builds I-ext tests
-rsync copies the stuff from riscof_work to work/riscv-arch-test
-
|
2023-02-14 10:40:29 -08:00 |
|
Kevin Kim
|
5fed4c2c87
|
updated python script to generate bash file
|
2023-02-11 11:08:11 -08:00 |
|
Kevin Kim
|
7e4fc40dc7
|
changed python file to use WALLY env variable
|
2023-02-11 00:30:56 +00:00 |
|
Kip Macsai-Goren
|
76593cb282
|
Added necessary files to make bit make and run bit manipulation tests as part of regression
|
2023-02-10 10:35:19 -08:00 |
|
David Harris
|
9a6d7bb16d
|
Added RVTEST_CASE to testgen header
|
2023-02-09 18:25:24 -08:00 |
|
David Harris
|
8fb513ad35
|
Moved test generators
|
2023-02-09 18:24:48 -08:00 |
|
David Harris
|
edbf962b5f
|
Test gen header
|
2023-02-09 18:14:26 -08:00 |
|
David Harris
|
44fef2f2a1
|
debug simulating, produing discrepancy
|
2023-02-06 16:47:56 -08:00 |
|
David Harris
|
4c219de13d
|
Fixed floating point crash in debug.S
|
2023-02-06 15:38:57 -08:00 |
|
David Harris
|
5256d3a625
|
More progress on debug.S, but it crashes in Spike
|
2023-02-04 09:59:22 -08:00 |
|
David Harris
|
43668a3fc5
|
Developing debug test
|
2023-02-04 08:31:47 -08:00 |
|
David Harris
|
2c69adc5f7
|
Started making debug testcase
|
2023-02-04 08:18:55 -08:00 |
|
David Harris
|
80f42a8638
|
Renamed regression to sim
|
2023-02-02 14:48:23 -08:00 |
|
David Harris
|
78eb90715c
|
Removed pipelined level of hierarchy
|
2023-02-02 14:14:11 -08:00 |
|
David Harris
|
4883351bd2
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-01-28 18:18:53 -08:00 |
|
Kip Macsai-Goren
|
ee1bcf62ee
|
Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts.
|
2023-01-28 17:29:35 -08:00 |
|
David Harris
|
d8f0e3dd70
|
Modified testgen to not produce reference outputs
|
2023-01-27 07:25:40 -08:00 |
|
David Harris
|
cea89f27cf
|
Removed unused WALLY test references
|
2023-01-27 07:25:04 -08:00 |
|
David Harris
|
2af94bf283
|
Removed unused reference files
|
2023-01-27 07:21:55 -08:00 |
|
David Harris
|
37ba3d0fcd
|
Removed f tests from rv32e
|
2023-01-27 06:15:20 -08:00 |
|
David Harris
|
7fbbed7927
|
Update riscof makefile to use rv32gc config
|
2023-01-27 05:57:58 -08:00 |
|
David Harris
|
b81b5781e1
|
Renamed spike_rv32imc_isa.yaml to rv32gc to reflect cases tested
|
2023-01-27 05:56:49 -08:00 |
|
David Harris
|
7d8a0d9615
|
Refactored setup QUESTA and SNPS paths, and removed troublesome bit manipulation test cases
|
2023-01-23 05:00:11 -08:00 |
|
David Harris
|
b173112f86
|
Continued framework for B instructions
|
2023-01-20 14:27:13 -08:00 |
|
Ross Thompson
|
97feea2f48
|
Possibly working speculative global history.
|
2023-01-08 23:46:53 -06:00 |
|
Ross Thompson
|
a35fb3addd
|
core part of global history works now. forwarding is still broken.
|
2023-01-08 23:35:02 -06:00 |
|
Ross Thompson
|
f8c656f1e0
|
Simiplified global history branch predictor.
|
2023-01-04 23:41:55 -06:00 |
|
Kip Macsai-Goren
|
964084f0b3
|
added fs=00 to status fp enabled test
|
2022-12-22 15:15:53 -08:00 |
|
Kip Macsai-Goren
|
d25d699800
|
Added status.tvm bit test that passes make and regression
|
2022-12-22 14:43:22 -08:00 |
|
Kip Macsai-Goren
|
a37bde7452
|
updated trap handler alignemnts to 64 bytes in priv tests
|
2022-12-22 14:23:04 -08:00 |
|
David Harris
|
ca949f2110
|
Only delegated bits of SIP are readable
|
2022-12-21 12:32:49 -08:00 |
|
Ross Thompson
|
f6393d1288
|
Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
|
2022-12-21 13:16:09 -06:00 |
|
Ross Thompson
|
c41d58bd29
|
Vectored interrupts now require 64 byte alignment.
Eliminates adder.
|
2022-12-21 12:05:49 -06:00 |
|
David Harris
|
00ff823d84
|
Restored rv32d arch test after new push
|
2022-12-20 10:56:33 -08:00 |
|
Ross Thompson
|
c3b77926d5
|
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
|
2022-12-18 18:30:35 -06:00 |
|
Ross Thompson
|
e8c1d14abb
|
Have a basic cache test to fill all ways and sets.
|
2022-12-18 17:20:30 -06:00 |
|
Ross Thompson
|
7a352edf13
|
Attempted to make a cache test.
|
2022-12-18 17:15:08 -06:00 |
|
Ross Thompson
|
9d1cb9337e
|
Updated tests for fpga and BP.
|
2022-12-18 16:24:26 -06:00 |
|
David Harris
|
643a2e7cf9
|
Use FPU divider for integer division when F is supported
|
2022-12-14 17:03:13 -08:00 |
|
Kip Macsai-Goren
|
55627f40e2
|
added passing GPIO test to 64 bit tests
|
2022-12-05 21:31:00 -08:00 |
|
Kip Macsai-Goren
|
4c81b6fa5f
|
added corrrect scr read out of uart to periph test
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
4ab99904a4
|
added all 32 bit tests to 64 bit periph tests except gpio
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
51e78d9e48
|
added copies of 64 bit tests to 32 bit periph and priv tests
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
540d6c2f41
|
added -01 to all WALLY tests
|
2022-12-05 20:16:02 -08:00 |
|
Ross Thompson
|
fc05e27416
|
Updated riscv arch test removed misaligned1.
|
2022-12-04 00:18:10 +00:00 |
|
Kip Macsai-Goren
|
9b1765ce92
|
added tests for invalid address being written to satp. Not passing regression
|
2022-11-27 13:22:35 -08:00 |
|
Kip Macsai-Goren
|
21e045eb7d
|
added potential fix to overrun error and fifo interrupt error. test passes
|
2022-11-06 22:01:02 -08:00 |
|
Kip Macsai-Goren
|
90ef371abc
|
fixed fifo timout handling. error now in data ready interrupt
|
2022-11-05 13:34:24 -07:00 |
|
Kip Macsai-Goren
|
c06da6e6fe
|
fixed broken instructions so make works.
|
2022-11-03 23:06:20 +00:00 |
|
Ross Thompson
|
f1eb20ef4d
|
Updated to put dtb into the rodata segment for our linker script.
|
2022-11-03 17:48:20 -05:00 |
|
Ross Thompson
|
1d7002e5c5
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-03 17:36:04 -05:00 |
|
Ross Thompson
|
ccce0df535
|
Potentially a valid zero stage boot loader based on cva6.
|
2022-11-03 17:35:57 -05:00 |
|
Ross Thompson
|
103514a8e0
|
More outline for uart timeout interrupt.
|
2022-10-28 13:53:56 -05:00 |
|
Ross Thompson
|
21eca47d2e
|
Untested change to uart test for outline of how to handle rx fifo timeout.
|
2022-10-28 13:31:16 -05:00 |
|
Kip Macsai-Goren
|
6e45698b86
|
Added test for UART FIFO timeout. Does not pass regression
|
2022-10-25 05:35:56 +00:00 |
|
Ross Thompson
|
a59df0c77d
|
Created one off test to replicate the floating point forwarding hazard bug.
|
2022-10-22 16:29:12 -05:00 |
|
Kip Macsai-Goren
|
c18c181fc0
|
fixed endianness mstatush problem, passes make, not regression
|
2022-10-04 17:37:39 +00:00 |
|
Kip Macsai-Goren
|
e603973dff
|
added xlen and endianness test edits. xlen passes but endinanness still won't make
|
2022-09-26 05:03:19 +00:00 |
|
Kip Macsai-Goren
|
9821a50eaa
|
added mstatus uxl, sxl bit tests (not tested in regression yet)
|
2022-09-18 00:11:29 +00:00 |
|
Kip Macsai-Goren
|
0cc7f5719c
|
ported endianness tests to 32 bits (not tested in regression yet)
|
2022-09-18 00:10:29 +00:00 |
|
Kip Macsai-Goren
|
c5cbe43732
|
Fixed typos in existing endianness test
|
2022-09-18 00:09:52 +00:00 |
|
Kip Macsai-Goren
|
e6987524ab
|
added full coverage of subword loads and stores to endianness test
|
2022-09-17 23:14:38 +00:00 |
|
Kip Macsai-Goren
|
cc7d1c8ef9
|
Created initial endianness tests
|
2022-09-16 01:06:26 +00:00 |
|
David Harris
|
898dbc8e74
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
|
2022-08-03 09:33:56 -07:00 |
|
David Harris
|
4fb467ee8a
|
Debugging plic-s test
|
2022-08-03 13:21:09 +00:00 |
|
David Harris
|
7e5b78f240
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
cab0349701
|
Started plic-s tests
|
2022-08-03 03:48:08 +00:00 |
|
David Harris
|
93d7d7179e
|
Added parity and stop bit tests to UART
|
2022-07-28 04:35:51 +00:00 |
|
David Harris
|
429bdae1c4
|
Fixed UART reference output
|
2022-07-27 22:16:38 +00:00 |
|
David Harris
|
b08c87cb47
|
Finished UART test
|
2022-07-27 04:06:59 +00:00 |
|
David Harris
|
75a265159b
|
Increased timeout threshold to avoid timeout building riscof tests on slow machine
|
2022-07-27 04:05:21 +00:00 |
|
slmnemo
|
7348af7fd5
|
Updated reference file for UART test
|
2022-07-26 09:39:31 -07:00 |
|
slmnemo
|
a9d5805990
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-26 09:15:20 -07:00 |
|
slmnemo
|
5218865a7f
|
Committing changes made to UART test
|
2022-07-26 09:14:40 -07:00 |
|
David Harris
|
2d7f4b133c
|
More work toward riscof tests
|
2022-07-26 06:19:13 -07:00 |
|
David Harris
|
c6a58eb5b6
|
Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
|
2022-07-25 16:23:10 -07:00 |
|
David Harris
|
416f5edfe0
|
More riscof makefile tuning
|
2022-07-25 21:15:56 +00:00 |
|
David Harris
|
7f7b3359b0
|
Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings
|
2022-07-25 20:50:38 +00:00 |
|
slmnemo
|
bfced6bfe8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-22 17:13:38 -07:00 |
|
slmnemo
|
ca4511b6dc
|
Fixed UART FIFO bugs and added FIFO tests
|
2022-07-22 17:13:19 -07:00 |
|
Daniel Torres
|
d0aaae26fe
|
fixed wally rv32e tests, updated regression makefile to new testflow
|
2022-07-22 17:09:46 -07:00 |
|
Daniel Torres
|
4da96c5791
|
fixed 32priv tests, now passing
|
2022-07-22 15:35:20 -07:00 |
|
Daniel Torres
|
24828db612
|
changes to test.vh for compatability
|
2022-07-22 15:00:48 -07:00 |
|
Daniel Torres
|
4198145ce2
|
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
|
2022-07-22 14:58:55 -07:00 |
|
slmnemo
|
141f2a40e4
|
UART updates and PMA fix
|
2022-07-22 14:49:03 -07:00 |
|
slmnemo
|
9cca567136
|
Added test comments to reference output
|
2022-07-22 12:35:59 -07:00 |
|
Daniel Torres
|
0e75142ef4
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-22 11:16:09 -07:00 |
|
Daniel Torres
|
95fdd408ee
|
commiting current changes to riscof wally tests
|
2022-07-22 11:14:04 -07:00 |
|
slmnemo
|
d38369e8bf
|
Added new PLIC and UART tests
|
2022-07-22 07:12:55 -07:00 |
|
slmnemo
|
df568fd202
|
Added PLIC and UART tests and new functions to the test library
|
2022-07-22 07:10:39 -07:00 |
|
Daniel Torres
|
8dcb794bbb
|
added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
|
2022-07-21 20:58:58 -07:00 |
|
Daniel Torres
|
635a02cf6a
|
made makefile more specific, just incase future additions
|
2022-07-21 12:50:02 -07:00 |
|