Ross Thompson
15f1627a31
Fixed interrupt delay bug by reverting CommittedM changes.
2021-12-28 22:27:12 -06:00
Ross Thompson
a966764d88
Removed CommittedM as it is redundant with LSUStall.
2021-12-28 16:14:10 -06:00
Ross Thompson
c2b0e61466
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
David Harris
0c57b61ace
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-20 21:09:20 -08:00
David Harris
001c39d8eb
Fixing paths in wally-setup.sh
2021-12-20 21:08:34 -08:00
Ross Thompson
53736096a6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
David Harris
193885c958
Moved generate of conditional units to hart
2021-12-19 17:03:57 -08:00
David Harris
1196e5c191
Moved generate statements for optional units into wallypipelinedhart
2021-12-19 16:53:41 -08:00
Ross Thompson
0257c08641
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
79ec4161b6
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
kwan
5ede8126fd
priviledge .* removed, passed regression
2021-12-13 00:34:43 -08:00
kwan
b05bc3c19e
test
2021-12-13 00:31:51 -08:00
kwan
83dae9d774
priviledge .* fixed, passed local regression
2021-12-13 00:22:01 -08:00
kwan
96ac298596
Priviledged .* removed
2021-12-12 09:55:45 -08:00
kwan
471f267987
Privilige .*s removed
2021-12-12 09:54:14 -08:00
Ross Thompson
cd59809e42
Fixed numerous errors in the preformance counter updates.
...
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
2021-12-09 11:44:12 -06:00
Ross Thompson
e43aa6ead4
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
d90d708cf9
activate STVAL for buildroot
2021-11-21 10:40:28 -08:00
David Harris
79c1395967
merging changes
2021-10-26 08:34:36 -07:00
David Harris
44de52a05a
Synchronous reset in non-flop blocks
2021-10-26 08:30:35 -07:00
bbracker
eb9740bc31
manually resolved git merge conflicts in testbench linux after checkpointing
2021-10-24 15:02:19 -07:00
bbracker
dcd4d9dd9f
add checkpointing to linux testbench
2021-10-24 06:47:35 -07:00
David Harris
88b2d9e687
lsu/ifu lint cleanup
2021-10-23 11:41:20 -07:00
David Harris
d0aa6911ff
random lint cleanup
2021-10-23 11:24:36 -07:00
David Harris
708b914a65
Lint cleanup from wallypipeliendhart
2021-10-23 10:29:52 -07:00
David Harris
6ae9aa7d80
lint cleanup: FPU and privileged
2021-10-23 09:41:24 -07:00
David Harris
80d2b9bc0d
subword read and csrc lint cleanup
2021-10-23 09:29:15 -07:00
David Harris
0eabd0ecc2
FMA and CSRC lint cleanup
2021-10-23 09:20:24 -07:00
David Harris
8b854bb1c2
Cleaned up LINT erors
2021-10-23 06:28:49 -07:00
Ross Thompson
09dc3e1143
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
David Harris
8d08ca6a1e
Changed some flops to settable
2021-10-18 17:05:29 -07:00
David Harris
df0b65e483
replaced flopenl with flopenr when clearing to 0
2021-10-18 16:53:18 -07:00
bbracker
5022647041
Revert "first attempt at verilog side of checkpoint functionality"
...
This reverts commit f6ef8e5656
2021-09-30 20:45:26 -04:00
bbracker
f6ef8e5656
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
Ross Thompson
99070127d8
Added debugging directives to system verilog.
2021-09-27 13:57:46 -05:00
David Harris
72c1cc33f5
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
David Harris
654f3d1940
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
2021-09-13 12:40:40 -04:00
bbracker
5e9a39e755
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
Ross Thompson
bb3e94d68a
Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.
2021-08-23 15:46:17 -05:00
Ross Thompson
97653e1aea
Wally previously was overcounting retired instructions when they were flushed.
...
InstrValidM was used to control when the counter was updated. However this is
not suppress the counter when the instruction is flushed in the M stage.
2021-08-23 12:24:03 -05:00
Ross Thompson
b6e2710f5d
Confirmed David's changes to the interrupt code.
...
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine. This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege. Since the CPU
is currently in machine mode the interrupt must be taken if MIE.
Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
2021-08-22 21:36:31 -05:00
David Harris
696be3ff68
possible interrupt code
2021-08-22 17:02:40 -04:00
Ross Thompson
4f3f26c5cb
Switched ExceptionM to dcache to be just exceptions.
...
Added test bench logic to hold forces until the W stage is unstalled.
2021-08-13 15:53:50 -05:00
Ross Thompson
d430659983
fixed the read timer issue but we still have problems with interrupts and i/o devices.
2021-08-06 10:16:06 -05:00
Kip Macsai-Goren
bb8ec549a7
fixed issue with tlbflush remaining high during a stalled sfence instruction
2021-07-21 17:43:36 -04:00
Ross Thompson
ae2371f2ce
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
bbracker
77b690faf0
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
2021-07-19 15:13:03 -04:00
David Harris
e3bf8db80b
trap.sv comment cleanup
2021-07-17 16:01:07 -04:00
David Harris
b2c2194478
trap.sv cleanup
2021-07-17 15:57:10 -04:00
David Harris
348e69c096
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:24:26 -04:00
