Ross Thompson 4f3f26c5cb Switched ExceptionM to dcache to be just exceptions. ... Added test bench logic to hold forces until the W stage is unstalled.		2021-08-13 15:53:50 -05:00
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csr.sv	Added performance counters for dcache access and dcache miss.	2021-07-19 22:12:20 -05:00
csrc.sv	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
csri.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
csrm.sv	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
csrn.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
csrs.sv	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
csrsr.sv	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
csru.sv	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
privdec.sv	Implemented TSR, TW, TVM, MXR status bits	2021-07-06 01:32:05 -04:00
privileged.sv	fixed issue with tlbflush remaining high during a stalled sfence instruction	2021-07-21 17:43:36 -04:00
trap.sv	Switched ExceptionM to dcache to be just exceptions.	2021-08-13 15:53:50 -05:00