cvw/wally-pipelined/src/privileged
2021-10-23 11:41:20 -07:00
..
csr.sv lsu/ifu lint cleanup 2021-10-23 11:41:20 -07:00
csrc.sv random lint cleanup 2021-10-23 11:24:36 -07:00
csri.sv fixed bug where M mode was sensitive to S mode traps 2021-09-07 19:14:39 -04:00
csrm.sv Changed some flops to settable 2021-10-18 17:05:29 -07:00
csrn.sv Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
csrs.sv Changed some flops to settable 2021-10-18 17:05:29 -07:00
csrsr.sv fixed the read timer issue but we still have problems with interrupts and i/o devices. 2021-08-06 10:16:06 -05:00
csru.sv Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
privdec.sv Implemented TSR, TW, TVM, MXR status bits 2021-07-06 01:32:05 -04:00
privileged.sv Lint cleanup from wallypipeliendhart 2021-10-23 10:29:52 -07:00
trap.sv lint cleanup: FPU and privileged 2021-10-23 09:41:24 -07:00