bbracker
8f4da826fb
plic subword access compliance
2021-04-04 23:10:33 -04:00
Katherine Parry
f41b5a2d38
Added missing files in FPU
2021-04-04 18:09:13 +00:00
bbracker
ce7b2314ef
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 06:40:53 -04:00
Thomas Fleming
5946b860ca
Comment out fpu from hart until module exists
2021-04-03 22:34:11 -04:00
Thomas Fleming
8f31e00f6a
Merge branch 'mmu' into main
...
Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-03 22:09:50 -04:00
Noah Boorstin
2f503ee6b9
busybear: temporary stop after 800k instrs
2021-04-03 21:37:57 -04:00
Thomas Fleming
e04ad8f304
Fix extraneous page fault stall
2021-04-03 21:28:24 -04:00
Thomas Fleming
35ba6f741b
Virtual memory test now turns on virtual memory
2021-04-03 21:24:06 -04:00
Jarred Allen
4ebc991a65
Fix bug in icache
2021-04-03 18:10:54 -04:00
Katherine Parry
08b31f7b2a
Integrated FPU
2021-04-03 20:52:26 +00:00
Ross Thompson
a743acd1fd
Partial fix to the integer divide stall issue.
2021-04-02 15:32:15 -05:00
James E. Stine
e38e7aff8e
Minor cleanup
2021-04-02 08:20:44 -05:00
James E. Stine
82cd900b65
Put back imperas testbench until figure out why m_supported is running for rv64ic
2021-04-02 08:19:25 -05:00
James E. Stine
9026357350
Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
2021-04-02 06:27:37 -05:00
Thomas Fleming
14cf331265
Merge branch 'main' into mmu
2021-04-01 16:29:39 -04:00
Thomas Fleming
06032936bd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-01 16:24:06 -04:00
Thomas Fleming
3f3d8f414d
Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu
2021-04-01 16:23:19 -04:00
Thomas Fleming
f9bf2fbc01
Implement sfence.vma and fix tlb writing
2021-04-01 15:55:05 -04:00
ushakya22
0b36284e95
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-01 15:49:00 -04:00
Jarred Allen
8dc57a7706
Begin changes to direct-mapped cache
2021-04-01 13:55:21 -04:00
Shreya Sanghai
bf3f4ff5b2
fixed minor bugs in localHistory
2021-04-01 13:40:08 -04:00
James E. Stine
59dee5580c
Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time.
2021-04-01 12:30:37 -05:00
ShreyaSanghai
e33007e30e
added localHistoryPredictor
2021-04-01 22:22:40 +05:30
ushakya22
5d9ed60646
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-01 02:04:57 -04:00
ushakya22
70d272d7e0
d
2021-04-01 02:04:02 -04:00
Shreya Sanghai
65e9747752
fixed bugs in global history to read latest GHRE
2021-03-31 21:56:14 -04:00
Teo Ene
6aed8eaea1
Updated MISA in coremark_bare config file
2021-03-31 20:39:02 -05:00
Noah Boorstin
4e62c7d5f5
busybear: temporarially stop checking CSRs
2021-03-31 14:14:32 -04:00
Noah Boorstin
679daeedf5
busybear: clean up questa warnings
2021-03-31 14:04:57 -04:00
Noah Boorstin
ddc56d8cd7
busybear: clean up questa warnings
2021-03-31 14:02:15 -04:00
Ross Thompson
f1107c5d7b
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
Ross Thompson
1e83810450
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Thomas Fleming
71d76e3b46
Remove virtual memory tests from rv32i folder
2021-03-30 22:51:52 -04:00
Thomas Fleming
9388a9f28a
Disable 'always-on' virtual memory
2021-03-30 22:49:47 -04:00
Thomas Fleming
e35020b7dc
Extend lint-wally to lint both rv32 and rv64
2021-03-30 22:42:28 -04:00
Thomas Fleming
e3d548d452
Merge remote-tracking branch 'origin/main' into main
...
Bring icache and MMU code together
Conflicts:
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2
Complete basic page table walker
2021-03-30 22:19:27 -04:00
Thomas Fleming
7f7cc73dd3
Update virtual memory tests and move to separate folder
2021-03-30 22:18:29 -04:00
Domenico Ottolia
d0a78b15b7
Add one more test to WALLY-CAUSE, and update privileged testgen
2021-03-30 19:44:58 -04:00
Domenico Ottolia
8c7e247b58
Add mcause tests to testbench
2021-03-30 17:17:59 -04:00
Domenico Ottolia
ae7868b166
Update privileged tests generator
2021-03-30 16:58:46 -04:00
Domenico Ottolia
47648dc721
Add all working mcause tests
2021-03-30 16:55:12 -04:00
ushakya22
bdd60c7934
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:36:30 -04:00
ushakya22
ba01d57767
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
ushakya22
2b99a7657a
privilege tests
2021-03-30 15:23:47 -04:00
James E. Stine
b2039e5b9a
Second update to divide that didn't get in for some silly git reason
2021-03-30 14:21:45 -05:00
James E. Stine
f4a533b6f6
Initial push of rv64imc and appropriate testbench
2021-03-30 14:21:02 -05:00
Ross Thompson
a3925505bf
fixed some bugs with the RAS.
2021-03-30 13:57:40 -05:00
Jarred Allen
6cda818f09
Merge branch 'cache2' into cache
...
Conflicts:
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 13:32:33 -04:00
