Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-27 15:04:36 +00:00
Code Issues Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
427 Commits 5 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
Python 19.3%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
7f7cc73dd3
Go to file
Thomas Fleming 7f7cc73dd3 Update virtual memory tests and move to separate folder
2021-03-30 22:18:29 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
.gitignore Add vscode and pycache folders to .gitignore 2021-03-25 02:37:50 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md

README.md

riscv-wally

Configurable RISC-V Processor