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Configurable RISC-V Processor
503 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
e3d548d452
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Thomas Fleming e3d548d452 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 22:24:47 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined Merge remote-tracking branch 'origin/main' into main 2021-03-30 22:24:47 -04:00
.gitignore busybear: stop NOPing out atomics 2021-03-25 13:29:56 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor