Domenico Ottolia
d5f86fadac
Add tests for sepc register
2021-04-20 23:50:53 -04:00
Ross Thompson
a861a37b72
Why was the linter messed up?
...
There are a number of combo loops which need fixing outside the icache. They may be fixed in main.
We get to instruction address 50 now!
2021-04-20 22:06:12 -05:00
Ross Thompson
daa1ab9261
Progress on icache. Fixed some issues aligning the PC with instruction. Still broken.
2021-04-20 21:19:53 -05:00
Ross Thompson
649589ee2c
Broken icache. Design is done. Time to debug.
2021-04-20 19:55:49 -05:00
Domenico Ottolia
e02ff60b07
Fix synthesis warnings for privileged unit (replace 'initial' settings)
2021-04-20 17:57:56 -04:00
Noah Boorstin
cd6cb1f66c
really small parser update
2021-04-19 23:17:37 -04:00
Noah Boorstin
c7a09d2359
yay buildroot passes a decent amount of tests now
...
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
2021-04-19 03:26:08 -04:00
Jarred Allen
59b340dac9
Merge branch 'main' into cache
2021-04-19 00:05:23 -04:00
Katherine Parry
204e5cb018
fixed synth bugs in fpu
2021-04-19 00:39:16 +00:00
Noah Boorstin
10c7ac7f73
slowly more buildroot progress
2021-04-18 18:18:07 -04:00
Noah Boorstin
d0a137ce0c
neat verilog thing
2021-04-18 17:48:51 -04:00
Noah Boorstin
0e71c212b2
buildroot parser: more updates
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5 -> 23 instructions!
2021-04-17 17:44:46 -04:00
Noah Boorstin
5902637632
buildroot: sim is now running!
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yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9
start to add buildroot testbench
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This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
Noah Boorstin
0931f0d977
busybear testgen updates
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and start working on qemu parser
2021-04-16 15:34:55 -04:00
Jarred Allen
3868a82932
dcache lints
2021-04-15 21:13:56 -04:00
Jarred Allen
32cfbc6926
Enable linting of blocks not yet in the hierarchy
2021-04-15 21:13:40 -04:00
bbracker
11cf251378
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 21:09:27 -04:00
bbracker
195cead01c
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00
Add tests for scause and ucause
2021-04-15 19:41:25 -04:00
Domenico Ottolia
a149f2f3d8
Add support for vectored interrupts
2021-04-15 19:13:42 -04:00
Domenico Ottolia
70b79ca301
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-15 16:57:27 -04:00
Domenico Ottolia
8c4cfa5f69
Add 32 bit privileged tests
2021-04-15 16:55:39 -04:00
Teo Ene
a9c6d357d8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-15 15:29:09 -05:00
Teo Ene
7a40c27b59
Quick fix to ahblite missing default statement done in class :)
2021-04-15 15:29:04 -05:00
Thomas Fleming
e8770e3eac
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Conflicts:
wally-pipelined/src/mmu/priority_encoder.sv
2021-04-15 16:20:43 -04:00
Thomas Fleming
e838f0bb3d
Change priority encoder to avoid extra assignment
2021-04-15 16:17:35 -04:00
Teo Ene
3b9895cfe9
Small update to synth scripts
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Writes out corrent timing reports
2021-04-15 14:24:39 -05:00
Domenico Ottolia
ee3e6b4aec
Fix bug in device/rv32p/Makefile.include so that 32-bit privileged tests will run
2021-04-15 14:50:03 -04:00
Thomas Fleming
2c4682c4be
Connect tlb and icache properly
2021-04-15 14:48:39 -04:00
Teo Ene
cefc8ea22b
Temporary change to mmu/priority_encoder.sv
...
Necessary to get synth working
Original HDL is still there, just commented out
2021-04-15 13:37:12 -05:00
Katherine Parry
0bdd3efdd5
integraded the FMA into the FPU
2021-04-15 18:28:00 +00:00
Jarred Allen
7b4b1a31ef
Merge branch 'main' into cache
2021-04-15 13:47:19 -04:00
Ross Thompson
534e3eaac8
Merge branch 'bpfixes' into main
2021-04-15 09:06:21 -05:00
Shreya Sanghai
75caa65df1
Cherry Pick merge of Shreya's localhistory predictor changes into main.
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fixed minor bugs in localHistory
2021-04-15 09:04:36 -05:00
ShreyaSanghai
80fbd66113
added localHistoryPredictor
2021-04-15 08:58:22 -05:00
Shreya Sanghai
3696bf4f2c
fixed bugs in global history to read latest GHRE
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Cherry pick Shreya's commits into main branch.
2021-04-15 08:55:22 -05:00
bbracker
76f50d7a69
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 09:06:03 -04:00
bbracker
da22308e60
csri lint improvement
2021-04-15 09:05:53 -04:00
David Harris
6e298962e9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-14 23:41:23 -04:00
David Harris
5112e50d5b
Deleted extraneous exe2memfile.pl
2021-04-14 23:41:15 -04:00
Jarred Allen
4d58f673b2
Add a comment to explain a detail
2021-04-14 23:14:59 -04:00
Thomas Fleming
d281ecd067
Remove imem from testbenches
2021-04-14 20:20:34 -04:00
Jarred Allen
c32fe09056
More icache bugfixes
2021-04-14 19:03:33 -04:00
Jarred Allen
757b64e487
Merge branch 'main' into cache
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Conflicts:
wally-pipelined/src/cache/dmapped.sv
wally-pipelined/src/cache/line.sv
wally-pipelined/src/ifu/icache.sv
2021-04-14 18:24:32 -04:00
bbracker
ccff1e6c99
rv64 interrupt servicing
2021-04-14 10:19:42 -04:00
Noah Boorstin
3e0ed5a2b1
busybear: use (slightly) less terrible verilog
2021-04-14 00:18:44 -04:00
Noah Boorstin
18a4d5fc8d
busybear testbench updates
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start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic
I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
2021-04-14 00:00:27 -04:00
Thomas Fleming
bb2d433971
Fix mmu lint errors
2021-04-13 19:19:58 -04:00
Thomas Fleming
e164437fe8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-13 17:56:56 -04:00
