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9471ccd2fc
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143 Commits

Author SHA1 Message Date
Rose Thompson
9471ccd2fc Updated Makefiles and source files to build the zsbl according to the config. 2024-09-02 14:03:47 -07:00
Rose Thompson
2e55f1cecc Well on the way to a fully automated FPGA build process which 
correctly sets the clocks and memory locations.
 2024-09-02 11:19:02 -07:00
Rose Thompson
f1d9e18dee Modified fpga config to support two fpga boards with different amount of memory. 
Modified vcu108 constraints to better constrain the spi clock and in/out.
 2024-08-29 16:12:58 -07:00
Rose Thompson
7e16ddd859 Improved fpga synth script. 2024-08-27 15:50:05 -07:00
Rose Thompson
e5d3462a90 Converted wall.tcl to entirely project mode. 2024-08-27 14:15:58 -07:00
Rose Thompson
f20a1564fa Added SPI debugger. 2024-08-26 17:22:13 -07:00
Rose Thompson
842aea157c Updated vc108 constraints for spi based sd card and setting 50 Mhz. 2024-08-23 15:59:11 -07:00
Rose Thompson
167878aee4 Commet out debug code in fpga synth script. 2024-08-23 14:46:01 -07:00
Rose Thompson
4d56b3ca96 Maybe improvements to fpga synthesis. 2024-08-23 13:00:22 -07:00
Rose Thompson
fc80bf1251 More updates to fpga IP module names. 2024-08-22 14:31:39 -07:00
Rose Thompson
8d40a0a092 Changed names of fpga IP modules to match textbook. Updated boot.h to 
use the correct clock speed for #DEFINE for UART in the zero stage
bootloader.
 2024-08-22 13:56:50 -07:00
Jordan Carlin
8ca4a5f20e
FPGA Makefile refactoring 2024-08-15 11:58:40 -07:00
David Harris
bc70f0b933
Merge pull request #869 from jordancarlin/installation 
Installation and setup overhaul
 2024-08-08 15:39:23 -07:00
Jacob Pease
8c96c06022 Commented out rvvi debug probes in wally.tcl. 2024-08-08 13:52:53 -05:00
Jordan Carlin
76eef03fe4
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-08-07 20:22:55 -07:00
Jacob Pease
954e21148f Removed line referring to local file in wally.tcl. 2024-08-06 17:11:08 -05:00
Jacob Pease
af2344d2d5 Merge branch 'main' of github.com:openhwgroup/cvw into spiboot 2024-08-06 17:09:39 -05:00
Jordan Carlin
42a9bbf28d
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-07-25 21:21:57 -07:00
Jacob Pease
ebdf25a53b Commented out references to old axi IP from wally.tcl. 2024-07-24 22:47:15 -05:00
Jacob Pease
2caf9e93be Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram. 2024-07-24 22:46:24 -05:00
Rose Thompson
b1a711ae0f Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. 2024-07-24 12:47:50 -05:00
Rose Thompson
556c210e76 Added option to use rvvi ila 2024-07-22 12:19:37 -05:00
Rose Thompson
0d40b8c933 Cleanup in prep to merge the rvvi branch into main. 2024-07-19 15:48:20 -05:00
Jordan Carlin
7419689359
Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability) 2024-07-03 20:42:55 -07:00
Ross Thompson
563980443a Merge branch 'main' into rvvi 2024-06-10 18:10:23 -07:00
Rose Thompson
38ddbf860e Fixed bug with mmcm not generating the 4th clock. 2024-05-30 16:19:28 -05:00
Jacob Pease
7ecd1c7d5f The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file. 2024-05-30 15:48:27 -05:00
Rose Thompson
9703055758 The FPGA is synthesizing with the rvvi and ethernet hardware. 2024-05-30 15:37:17 -05:00
Rose Thompson
8123695831 Maded insert_debug_comment.sh compatible with cygwin. 2024-04-22 10:48:34 -05:00
Rose Thompson
3bed733301 Fixed fpga to work with the updated regression changes. 2024-04-22 10:42:01 -05:00
Rose Thompson
c1221e6608 Fixed insert_debug_comment.sh to work with the older version of bash. 2024-04-16 10:55:26 -05:00
Rose Thompson
cc7f433ce0 Update the fpga scripts to use the new derivative configs. 2024-01-31 13:19:28 -06:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
Rose Thompson
26cd22c388 Replaced fpga's verilog top with system verilog. 2023-12-15 13:42:52 -06:00
Rose Thompson
dab9d7ab3c Replaced fpga top level verilog with system verilog. 2023-12-15 13:07:08 -06:00
Rose Thompson
34631c54d3 Get's the fpga building again after the git history rewrite. 2023-12-14 17:08:25 -06:00
Jacob Pease
7e494f2d3b Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile. 2023-12-01 18:59:18 -06:00
Jacob Pease
71066cae12 Modified FPGA Makefile to override with relative path. FPGA boots now. 2023-11-30 17:51:15 -06:00
Jacob Pease
ff73f798ed Replaced vivado-risc-v addins directory with new SDC repo. 2023-11-16 13:59:12 -06:00
Rose Thompson
d4bc9da085 Fixed another bug in the updated script changes. 2023-11-13 18:12:02 -06:00
Rose Thompson
f8b65f50b0 Fixed bugs in the updated fpga synthe script. 2023-11-13 18:10:22 -06:00
Rose Thompson
d5f0c15b90 Modified the fpga build script to generate it's own config file rather than use the one in config/fpga. 2023-11-13 17:48:28 -06:00
Rose Thompson
6b7ff50a84 Reduced Arty A7 clock speed to 20Mhz to support Zicclsm. 2023-11-13 16:44:02 -06:00
Ross Thompson
055e00b8ac Pushed vcu118 to 71MHz. 2023-08-25 17:04:50 -05:00
Jacob Pease
2bf6207919 Added help option to the flash-sd script. 2023-08-22 13:37:33 -05:00
Ross Thompson
cab40e618f Updateds to vcu118 constraints and device tree. 2023-08-02 16:51:32 -05:00
Ross Thompson
fb1c1a1832 Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails. 2023-08-02 16:14:04 -05:00
Ross Thompson
c4ae856f92 Clean up vcu118 synth scripts. 2023-08-01 14:39:33 -05:00
Ross Thompson
06efd2cdde Pushed performance of arty a7 to 23Mhz. 2023-07-31 14:13:09 -05:00
Jacob Pease
9d33e08dbb Removed non-existent SDC dependency from VCU targets in FPGA Makefile. 2023-07-27 15:01:20 -05:00