Rose Thompson e5d3462a90 Converted wall.tcl to entirely project mode.		2024-08-27 14:15:58 -07:00
..
debug	Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.	2022-10-24 15:38:39 -05:00
ahbaxibridge.tcl	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
bootrom.txt	Added bootrom.txt.	2022-03-30 17:29:48 -05:00
clkconverter.tcl	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
ddr3-ArtyA7.tcl	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
ddr4-vcu108.tcl	Updated vc108 constraints for spi based sd card and setting 50 Mhz.	2024-08-23 15:59:11 -07:00
ddr4-vcu118.tcl	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
insert_debug_comment.sh	Maded insert_debug_comment.sh compatible with cygwin.	2024-04-22 10:48:34 -05:00
Makefile	Maybe improvements to fpga synthesis.	2024-08-23 13:00:22 -07:00
mmcm.tcl	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
probe	Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)	2024-07-03 20:42:55 -07:00
sysrst.tcl	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
wally.tcl	Converted wall.tcl to entirely project mode.	2024-08-27 14:15:58 -07:00
wave_config.wcfg	Updateds to vcu118 constraints and device tree.	2023-08-02 16:51:32 -05:00
xlnx_ddr3-artya7-mig.prj	It's almost working.	2023-04-18 14:24:59 -05:00
xlnx_ddr4.tcl	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00