Rose Thompson
92ee56c1a1
Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV.
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testbench.sv was missing the trace2cov instance.
2024-05-27 17:25:20 -05:00
Rose Thompson
4c0261fd2c
Closer. Needed to reorder includes and defines.
2024-05-27 15:37:16 -05:00
Rose Thompson
ff611016c7
Closer?
2024-05-27 14:11:02 -05:00
Rose Thompson
26c6eec832
Getting closer to functional coverage integration.
2024-05-27 13:20:18 -05:00
Rose Thompson
2985cfb7eb
Preliminary work to merge functional coverage into wally.do.
2024-05-27 11:59:13 -05:00
Rose Thompson
c9b59c8b99
Merge pull request #815 from quswarabid/covergen
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Covergen
2024-05-27 10:42:29 -05:00
Quswar Abid
997b5901cc
sb types are all passing, loaditypes are not!
2024-05-27 04:27:50 -07:00
Quswar Abid
1bf9b13953
added some sb types
2024-05-27 03:58:38 -07:00
Quswar Abid
29d7cd5663
unwanted comments
2024-05-27 03:58:38 -07:00
Quswar Abid
8edc4057ed
compilable tests generating for loaditypes[lb, lh, lw, ld, lbu, lhu, lwu]
2024-05-27 03:58:38 -07:00
David Harris
14b9223390
Merge pull request #813 from jordancarlin/fround_fixes
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Fround fixes
2024-05-26 23:54:21 +02:00
Jordan Carlin
6f7a802b86
Merge branch 'main' of https://github.com/openhwgroup/cvw into fround_fixes
2024-05-26 14:40:26 -07:00
Jordan Carlin
b830d20f2d
Modify Fround Tmask to work for X=1
2024-05-25 12:56:02 -07:00
Rose Thompson
153e66c4bb
Merge pull request #810 from davidharrishmc/dev
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Zk simplification
2024-05-25 11:52:56 -05:00
Jordan Carlin
fb77440a64
Update fpctrl fmt to work for fround instructions
2024-05-24 15:33:45 -07:00
Jordan Carlin
ae29a9b861
Update control bits for froundnx
2024-05-24 15:19:20 -07:00
David Harris
cfe83f5b49
Added derived configs to test Zb* and Zk* individually
2024-05-24 15:18:36 -07:00
Jordan Carlin
dcafe4793e
Add froundnx and fround.d tests
2024-05-24 15:16:35 -07:00
David Harris
a95977590d
AES cleanup
2024-05-24 14:28:30 -07:00
David Harris
b2689b4f01
AES cleanup
2024-05-24 14:13:57 -07:00
David Harris
ec5c67a5c1
AES cleanup
2024-05-24 13:48:53 -07:00
David Harris
e626052ec9
simplified AES32de mixcolumns because input is only one byte
2024-05-23 22:30:25 -07:00
David Harris
b0d1344121
Commented sha instructions
2024-05-23 22:06:37 -07:00
Rose Thompson
5b7b23fd64
Merge pull request #812 from jordancarlin/revert-811-dev
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Revert "Remove existing derived configs before creating new ones" and remove in derivgen.pl instead
2024-05-23 16:05:19 -05:00
Jordan Carlin
a1e22adc1e
Delete deriv directory in derivgen.pl before remaking derived configs
2024-05-23 14:01:13 -07:00
Jordan Carlin
6a2192db6e
Revert "Remove existing derived configs before creating new ones"
2024-05-23 13:56:38 -07:00
Rose Thompson
fc6814909d
Merge pull request #811 from jordancarlin/dev
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Remove existing derived configs before creating new ones
2024-05-23 15:28:59 -05:00
Jordan Carlin
fb8e97dd04
Remove existing derived configs before creating new ones
2024-05-23 13:17:24 -07:00
David Harris
ac153bc4ed
More simplifying sha512_32
2024-05-23 05:46:56 -07:00
David Harris
d9a1691c83
Simplified sha512_32
2024-05-23 05:39:50 -07:00
David Harris
c160ced2d2
Zk* cleanup
2024-05-22 15:01:20 -07:00
David Harris
3ad815ce34
Reordered Zicond support in ALU
2024-05-22 08:29:08 -07:00
David Harris
a17204b0fe
Continued bmu cleanup
2024-05-22 00:48:04 -07:00
David Harris
88eb7bd045
Pulled brev8 out of byteop so redundant byteop logic is not needed in zbkb
2024-05-22 00:22:53 -07:00
David Harris
af75140bbc
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-05-21 00:50:15 -07:00
David Harris
d9ac37d771
Merge pull request #807 from ross144/main
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Improved README
2024-05-21 09:48:30 +02:00
Rose Thompson
d6b4a1fc83
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-20 16:23:57 -05:00
Rose Thompson
d025bd0aff
More improvements to the readme.
2024-05-20 16:23:25 -05:00
Rose Thompson
33eb5980e7
More readme formating.
2024-05-20 15:57:45 -05:00
Rose Thompson
7cc1fcbd49
More formating.
2024-05-20 15:52:36 -05:00
Rose Thompson
55008e98c9
Formated readme.
2024-05-20 15:50:17 -05:00
Rose Thompson
ad568e9d25
Updated readme.
2024-05-20 15:46:26 -05:00
David Harris
c32090067f
Merge pull request #806 from ross144/main
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Merge testbench-imperas.sv into testbench.sv
2024-05-18 06:28:29 +01:00
Rose Thompson
6e3ccbb9c1
Almost have it working for both buildroot and single elfs.
2024-05-17 17:34:29 -05:00
Rose Thompson
224b2e4dc4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-17 17:10:28 -05:00
Rose Thompson
e008999030
wsim now supports lockstep and single elf
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example
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --elf --lockstep
2024-05-17 17:10:15 -05:00
Rose Thompson
0ed75a3ff5
Reverted testbench-imperas.sv incase someone wants this.
2024-05-17 16:48:29 -05:00
Rose Thompson
038aae388b
Yay. Finally found the issue with the integrated testbench.sv and imperasDV.
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The function which loads the elf file rvviRefInit must be called during an initial block
using a valid file name. Because of how the testbench was organized the elffile was not defined
until several cycles later so the call to rvviRefInit did not have a valid elf. Waiting several
cycles does not work. rvviRefInit requires being called in an initial block so it is not possible
to run back to back imperasDV simulations in the same run.
2024-05-17 16:45:01 -05:00
Rose Thompson
e6902eb4d2
Ok. How does it still work? testbench-imperas.sv the same as testbench.sv now.
2024-05-17 16:08:14 -05:00
Rose Thompson
d9807bb909
This is crazy. I'm merging testbench.sv into testbench-imperas.sv to find the point when it stops working. But each logical point where it would stop working it keeps working. For example moving readmemh from initial to always block.
2024-05-17 14:45:37 -05:00
