Ross Thompson
e43aa6ead4
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
Ross Thompson
b8572d6a2a
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
David Harris
14e6d2c576
Converted flops to synchronous reset now that reset signal is synchronized
2021-10-25 11:49:20 -07:00
David Harris
bf3eb7b814
update scripts for handling src/*/* subdirectories
2021-10-23 08:54:29 -07:00
David Harris
7732d38c36
lint cleaning and moved files into subdirectories
2021-10-23 08:53:32 -07:00
Ross Thompson
09dc3e1143
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
David Harris
8d08ca6a1e
Changed some flops to settable
2021-10-18 17:05:29 -07:00
Ross Thompson
5fdac9fa3b
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
Ross Thompson
3d9d4cc03f
Partially working sd card reader.
2021-10-11 10:23:45 -05:00
David Harris
a077735ecc
Major reorganization of regression and simulation and testbenches
2021-10-10 15:07:51 -07:00
David Harris
dcbbee6623
More divider cleanup
2021-10-03 00:20:35 -04:00
David Harris
d532bde931
Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division
2021-10-02 10:36:51 -04:00
David Harris
35e5a5cef3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 23:15:34 -04:00
bbracker
5022647041
Revert "first attempt at verilog side of checkpoint functionality"
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This reverts commit f6ef8e5656
2021-09-30 20:45:26 -04:00
David Harris
a39e14663d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 20:07:43 -04:00
David Harris
e1ad732178
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
bbracker
f6ef8e5656
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
Ross Thompson
d4f514010d
Changes to make fpga synthesizable.
...
Added preload to test simple program on wally in fpga.
2021-09-22 10:54:13 -05:00
Ross Thompson
225657b8f9
Fixed bug with or_rows.
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If ROWS == 1 then the output was always X. Fixed by adding if to check if ROWS==1.
2021-09-11 15:51:11 -05:00
David Harris
30e2ec3987
Added testbench-arch for riscv-arch-test suite
2021-09-08 15:59:40 -04:00
David Harris
cf1e458ccf
simplified or_rows generation and renamed oneHotDecoder to onehotdecoder
2021-08-25 06:46:41 -04:00
David Harris
d6f859da18
renamed or_rows.sv
2021-07-16 20:17:03 -04:00
Ross Thompson
4549a9f1c9
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
3092e5acdf
Forgot to include one hot decoder.
2021-07-14 15:46:52 -05:00
David Harris
283c2cda0e
added or.sv
2021-07-13 13:26:40 -04:00
David Harris
57e1111df3
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
David Harris
c897bef8cd
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 01:19:38 -04:00
Teo Ene
1d5d7a7840
Flow updated for 90nm
2021-07-01 13:32:42 -05:00
David Harris
aef408af58
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
Katherine Parry
e4db6ea6f5
fixed lint warnings for fpu and lzd
2021-06-05 12:06:33 -04:00
Ross Thompson
db2a38c300
Fixed a few lint errors,
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clock gater was wrong,
missing signal definitions in branch predictor.
2021-06-02 09:33:24 -05:00
Ross Thompson
7afbd8d877
The clock gater was not implemented correctly. Now it is level sensitive to a low clock.
2021-06-01 15:05:22 -05:00
Ross Thompson
8e330367ac
added clock gater to floating point divider to speed up simulation time.
2021-06-01 13:46:21 -05:00
James E. Stine
889b935630
Modify elements of generics for LZD and shifter wrote for integer
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divider.
2021-05-31 08:36:19 -04:00
Noah Boorstin
2d1f63b590
change flop in ahb controller to use normal flop module
2021-03-10 19:14:02 +00:00
David Harris
6f4e8b723e
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
David Harris
cd4ba8831c
Merged bus into main
2021-02-25 00:28:41 -05:00
David Harris
adc5d5bc1a
Added MUL
2021-02-15 22:27:35 -05:00
David Harris
cc42655789
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
David Harris
07af481b67
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
