cvw/wally-pipelined/src/generic
2021-09-08 15:59:40 -04:00
..
clockgater.sv Fixed a few lint errors, 2021-06-02 09:33:24 -05:00
flop.sv Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
lzd.sv Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
mux.sv Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
onehotdecoder.sv simplified or_rows generation and renamed oneHotDecoder to onehotdecoder 2021-08-25 06:46:41 -04:00
or_rows.sv Added testbench-arch for riscv-arch-test suite 2021-09-08 15:59:40 -04:00
shift.sv Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00