mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
b8572d6a2a
Removed the need to use async flip flops in SDC. Added arrs, a synchronizer for reset. I think this works with the real FPGA hardware. The last build did not include this arrs but it worked. |
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| .. | ||
| adder.sv | ||
| arrs.sv | ||
| clockgater.sv | ||
| counter.sv | ||
| flop.sv | ||
| lzd.sv | ||
| mux.sv | ||
| neg.sv | ||
| onehotdecoder.sv | ||
| or_rows.sv | ||
| shift.sv | ||