David Harris
|
0419b5484a
|
parameterized register names in peripherals
|
2024-04-21 07:43:01 -07:00 |
|
David Harris
|
00a1c0fc57
|
Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors
|
2024-04-21 00:02:15 -07:00 |
|
David Harris
|
1817ab2e11
|
testbench import is happy now for Questa, but throws lint warning for VCS
|
2024-04-20 23:13:13 -07:00 |
|
David Harris
|
fd6a6b2249
|
environment variable cleanup
|
2024-04-20 22:52:08 -07:00 |
|
David Harris
|
f39e240082
|
Spacing cleanup
|
2024-04-20 20:53:49 -07:00 |
|
David Harris
|
25a26656b6
|
Removed unnecessary ZBB from BMU extract mux
|
2024-04-20 20:53:14 -07:00 |
|
David Harris
|
a1876b1e7c
|
script cleanup
|
2024-04-20 17:22:31 -07:00 |
|
David Harris
|
338f37b570
|
Moved getenv/getenvval declaration to config-shared so lint and regression both run
|
2024-04-20 17:19:42 -07:00 |
|
David Harris
|
571b67f565
|
Merging PR738
|
2024-04-20 17:15:17 -07:00 |
|
David Harris
|
e467e46967
|
Merge pull request #738 from slmnemo/linux_nightly
Added full Linux boot to regression-wally
|
2024-04-20 17:08:43 -07:00 |
|
slmnemo
|
f0229e970b
|
Fixed getenvvar verilator bug in rom1p1r, Removed unused system function from testbench.
|
2024-04-20 17:07:54 -07:00 |
|
slmnemo
|
66a002d879
|
Removed unused rmCmd string declaration
|
2024-04-20 16:58:23 -07:00 |
|
slmnemo
|
354d447269
|
Changed testbench to use fopen instead of opening and closing uartfile whenever writing
|
2024-04-20 16:56:54 -07:00 |
|
slmnemo
|
770d918268
|
Split buildroot and buildrootboot into separate tests to prevent squashing. Removed extraneous comments.
|
2024-04-20 16:39:05 -07:00 |
|
slmnemo
|
04ac4007ec
|
Updated tuple to name logfile to grepfile to better reflect purpose in regression. Added -a to grep so it works iwth binary files
|
2024-04-20 16:08:08 -07:00 |
|
David Harris
|
ea344fe2fa
|
Fixed getenvval lint error in rom1p1r
|
2024-04-20 15:55:52 -07:00 |
|
David Harris
|
a3db61b2b2
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2024-04-20 15:41:42 -07:00 |
|
slmnemo
|
6458fa5642
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into linux_nightly
|
2024-04-20 14:46:35 -07:00 |
|
David Harris
|
f639cf4d47
|
wsim invokes vcs
|
2024-04-20 14:23:21 -07:00 |
|
David Harris
|
3cb5cd0cb1
|
simulator cleanup
|
2024-04-20 14:12:55 -07:00 |
|
David Harris
|
800bdc290f
|
Increased ulimit for Verilator
|
2024-04-20 13:40:30 -07:00 |
|
David Harris
|
f790d67aa7
|
Merge pull request #745 from Karl-Han/rom_wally_env
Add getenvval for rom. Related to issue #723.
|
2024-04-20 13:29:28 -07:00 |
|
David Harris
|
b7e66ec7d6
|
Added Zcb tests to riscof
|
2024-04-20 13:17:33 -07:00 |
|
David Harris
|
d9ebfdfc4f
|
Enabled Zcb tests
|
2024-04-20 13:16:54 -07:00 |
|
David Harris
|
9ec4c752f1
|
Fixed bugs in Zcb compressed loads and stores
|
2024-04-20 13:16:31 -07:00 |
|
David Harris
|
0fc66268f8
|
coremark sweep cleanup
|
2024-04-20 12:44:44 -07:00 |
|
David Harris
|
c8e7a6990d
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2024-04-20 11:44:27 -07:00 |
|
David Harris
|
bf2f6859e4
|
Changed Verilog makefile to print transcript to stdout by default like Questa; redirected to logfile elsewhere
|
2024-04-20 11:27:54 -07:00 |
|
David Harris
|
84e8d86d2a
|
Merge pull request #739 from Karl-Han/deriv_support
Add extra path to search for deriv/buildroot
|
2024-04-20 11:23:54 -07:00 |
|
slmnemo
|
9e3622b4ec
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into linux_nightly
|
2024-04-20 11:23:33 -07:00 |
|
Rose Thompson
|
408af3cac3
|
Merge pull request #744 from quswarabid/update_addins
updated the submodules -> riscv-arch-tests and riscv-dv
|
2024-04-18 12:31:11 -05:00 |
|
Kunlin Han
|
08dd2eac74
|
Add getenvval for rom. Related to issue #723.
|
2024-04-17 23:26:09 -07:00 |
|
Rose Thompson
|
f94aab2d0d
|
Merge pull request #743 from quswarabid/tb_fix_uncore
the fix in testbench-imperas for uncore part of soc (unresolved reference)
|
2024-04-17 12:56:27 -05:00 |
|
slmnemo
|
2b0cf90a99
|
Merged with merge conflict
|
2024-04-17 10:47:28 -07:00 |
|
slmnemo
|
d39f1ebefc
|
Less hacky implementation of simulation log and searched log
|
2024-04-17 10:41:12 -07:00 |
|
slmnemo
|
b5ef66dc3c
|
Less hacky implementation of the same method as before
|
2024-04-17 10:26:30 -07:00 |
|
Quswar Abid
|
6f16b7e0c9
|
updated the submodules -> riscv-arch-tests and riscv-dv
|
2024-04-17 10:25:36 -07:00 |
|
Kunlin Han
|
91a88fa46c
|
Update sim/verilator/Makefile with more comments and merging variables.
|
2024-04-17 09:52:54 -07:00 |
|
Quswar Abid
|
1b18568d87
|
the fix Rose provided in meeting
|
2024-04-17 09:39:21 -07:00 |
|
David Harris
|
9a29668d1e
|
Merge pull request #737 from ross144/main
Fixed code coverage for regression-wally
|
2024-04-17 08:37:15 -06:00 |
|
Rose Thompson
|
416b138cf5
|
Merge pull request #740 from davidharrishmc/dev
Simplify shiftcorrection module
|
2024-04-17 09:19:30 -05:00 |
|
David Harris
|
7abf98cb4d
|
Reordered coremark sweep to match text
|
2024-04-17 04:03:48 -07:00 |
|
David Harris
|
c11daf43f0
|
removed extranious iteration flag from makefile
|
2024-04-17 04:02:58 -07:00 |
|
David Harris
|
45c32bbcdf
|
Fixed zbc to zbs to use full bit manipulation instructions in CoreMark
|
2024-04-17 04:02:06 -07:00 |
|
David Harris
|
5fdf8dfbec
|
Switched back to unsigned ints for RV32 CoreMark per spec. CM/MHz rises from 3.35 to 3.36
|
2024-04-17 04:01:25 -07:00 |
|
David Harris
|
3ea16c6057
|
Removed note about store stall being depricated
|
2024-04-17 03:34:11 -07:00 |
|
David Harris
|
cd9c2e0e2b
|
Updated embench Makefile to refer to generic sim, rather than modelsim
|
2024-04-17 03:16:01 -07:00 |
|
David Harris
|
0ff478d2a1
|
Updated CoreMark benchmark to default to rv32 for better numbers
|
2024-04-17 03:15:20 -07:00 |
|
David Harris
|
1d555cdbc3
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2024-04-17 03:01:14 -07:00 |
|
David Harris
|
db330b35b2
|
Removed unnecessary muxes from shiftcorrection; changed flag to --nightly in lint-wally
|
2024-04-16 20:57:49 -07:00 |
|