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7494 Commits

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Author SHA1 Message Date
Rose Thompson
8235f66af8 Merge pull request #468 from davidharrishmc/dev 
Divider optimization
 2023-11-12 20:05:44 -08:00
David Harris
571c7d3be4 Divider cleanup 2023-11-12 19:41:12 -08:00
David Harris
f437336540 Explained sqrt preshifting 2023-11-12 10:05:54 -08:00
David Harris
7c50b2c571 Renamed qsel to uslc and simplified radix2 uslc 2023-11-12 06:36:57 -08:00
David Harris
002034845a fdivsqrt comment improvements 2023-11-12 06:15:47 -08:00
Rose Thompson
4c2a9c7bab Merge pull request #467 from davidharrishmc/main 
Sanity in FDIVSQRT bit counts
 2023-11-11 16:37:25 -08:00
David Harris
6ac83c776e Cleaned up number of bits in fdivsqrt 2023-11-11 15:50:06 -08:00
David Harris
2bf5143163 Bug fixes related to size of fpdivsqrt bit count and number of cycles 2023-11-11 05:58:53 -08:00
David Harris
448ced00c5 Fixed testbench-fp to reflect signal name changes 2023-11-11 04:05:34 -08:00
Rose Thompson
0d6fb879aa Merge pull request #466 from stineje/main 
Add pap runs for sweep
 2023-11-10 22:25:55 -08:00
Rose Thompson
3af8e1ff50 Merge pull request #465 from davidharrishmc/dev 
fdivsqrt cleanup
 2023-11-10 22:25:09 -08:00
James E. Stine
7b79d8edeb Update scripts/synth.tcl to add with parameter for width and also checks wrapper to see if running CONFIG=rv32e to run without WIDTH 2023-11-10 21:10:35 -06:00
James E. Stine
65e536e401 Update ppa/ppaSynth.py for sky130 and better sweep parameterization 2023-11-10 21:07:36 -06:00
James E. Stine
e1c935bd9b Add bestSynths.csv that are the initial values. If this is re-run after ppaAnalysis.py is run, more refinement can be made 2023-11-10 21:06:24 -06:00
James E. Stine
91d7790251 update README for ppaSynth.py 2023-11-10 21:05:42 -06:00
David Harris
d5ba8fc5e6 fdivsqrt parameter cleanup 2023-11-10 18:33:08 -08:00
David Harris
3cae2385ab Simplified out LOGRK parameter 2023-11-10 18:19:41 -08:00
David Harris
7d0d9dcebe divider cleanup 2023-11-10 18:01:13 -08:00
David Harris
03864642a7 fdivsqrt cleanup 2023-11-10 16:42:32 -08:00
David Harris
c5b12b7331 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-10 16:40:54 -08:00
Rose Thompson
c8cca8dfb8 Simplification. 2023-11-10 18:39:36 -06:00
Rose Thompson
9dfe421c55 Yay! Zicclsm passes my regression test now. 2023-11-10 18:28:51 -06:00
Rose Thompson
c0e02ae190 Found another bug in the RTL's Zicclsm alignment. 2023-11-10 18:26:55 -06:00
Rose Thompson
02ab9fe99c Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues. 2023-11-10 17:58:42 -06:00
Rose Thompson
bd866e1025 Fixed some more bugs in the Zicclsm signature. 2023-11-10 17:36:10 -06:00
Rose Thompson
efecb0c346 Fixed bug in the Zicclsm test. 2023-11-10 17:34:23 -06:00
Rose Thompson
84d86b1994 Fixed spill bugs in the aligner. 2023-11-10 17:18:45 -06:00
Rose Thompson
ada354f443 Fixed bug in the misaligned access test. 2023-11-10 17:02:15 -06:00
David Harris
3108b58290 Simplified integer postnormalization shift 2023-11-10 14:55:36 -08:00
David Harris
b315ead575 Simplified IntDivNormShift 2023-11-10 14:28:57 -08:00
Rose Thompson
b74bfbeefd Merge branch 'main' into Zicclsm 2023-11-10 16:15:32 -06:00
Rose Thompson
baacb6f6eb Missed tests.vh. 2023-11-10 16:10:10 -06:00
Rose Thompson
9abd26aad9 Fixed bug which broke the non Zicclsm configs. 2023-11-10 16:08:04 -06:00
David Harris
2903791820 Simplified cycle count logic 2023-11-10 14:00:27 -08:00
David Harris
8f87860146 Reduced duplicated logic in fdivsqrtcycles 2023-11-10 11:25:54 -08:00
David Harris
255873a50c Divsqrt cleanup: change Q to U, commenting code 2023-11-10 11:21:02 -08:00
David Harris
953c53d065 fdivsqrt parameter cleanup 2023-11-10 09:11:15 -08:00
Rose Thompson
e1a7c7986a Merge pull request #463 from davidharrishmc/dev 
Dev
 2023-11-10 08:48:07 -08:00
David Harris
4c106215f4 Started cleaning up shifting leading 1 in fdivsqrt 2023-11-10 08:46:55 -08:00
David Harris
426aabbc1a Imperas commenting 2023-11-10 08:26:32 -08:00
David Harris
7e00581187 Add Svadu support and SPI to imperas configuration 2023-11-10 06:27:25 -08:00
David Harris
d7ced56c60 Merge pull request #460 from naichewa/main 
removed vestigial logic, added comments, deleted unused signals
 2023-11-10 05:18:57 -08:00
naichewa
5ce16dcb63 Cleanup 2023-11-09 16:52:55 -08:00
naichewa
3052a68d84 Remove old 2/4 bit logic, add comments, 
clean up unused signals
 2023-11-09 16:48:11 -08:00
David Harris
bae3772548 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-09 10:33:25 -08:00
Rose Thompson
1d2eccc14d Merge pull request #458 from stineje/main 
fix to setup.csh and also ppaSynth.py
 2023-11-09 10:20:05 -08:00
David Harris
625652b9ca Reporting stall path in synthesis script, support Zcb in Imperas 2023-11-09 06:59:29 -08:00
James E. Stine
9a47667fd7 update README on ppa 2023-11-09 01:00:33 -06:00
James E. Stine
5a115bc6f2 update ppaSynth.py with runCommand 2023-11-09 00:52:40 -06:00
James E. Stine
a6bc69d73f Add encoding for utf-8 on wrapperGen.py to avoid issue with incorrect encoding on RHEL C-shell 2023-11-08 23:57:59 -06:00