James E. Stine
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7b79d8edeb
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Update scripts/synth.tcl to add with parameter for width and also checks wrapper to see if running CONFIG=rv32e to run without WIDTH
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2023-11-10 21:10:35 -06:00 |
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James E. Stine
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65e536e401
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Update ppa/ppaSynth.py for sky130 and better sweep parameterization
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2023-11-10 21:07:36 -06:00 |
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James E. Stine
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e1c935bd9b
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Add bestSynths.csv that are the initial values. If this is re-run after ppaAnalysis.py is run, more refinement can be made
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2023-11-10 21:06:24 -06:00 |
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James E. Stine
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91d7790251
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update README for ppaSynth.py
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2023-11-10 21:05:42 -06:00 |
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James E. Stine
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9a47667fd7
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update README on ppa
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2023-11-09 01:00:33 -06:00 |
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James E. Stine
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5a115bc6f2
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update ppaSynth.py with runCommand
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2023-11-09 00:52:40 -06:00 |
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James E. Stine
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a6bc69d73f
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Add encoding for utf-8 on wrapperGen.py to avoid issue with incorrect encoding on RHEL C-shell
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2023-11-08 23:57:59 -06:00 |
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James E. Stine
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41f4c634b0
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Update to ppaSynth and ppaAnalyze - still have to push in mod for ppaAnalyze to plot more refined plots as well as some other plots - I have a fix working - just need to push in which will do later today
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2023-11-08 14:00:36 -06:00 |
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James E. Stine
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f83188a4a4
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add typo on setting WALLY for C-shell that caused some incompatability issues
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2023-11-08 13:59:04 -06:00 |
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Rose Thompson
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44c60a3e76
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Merge pull request #455 from davidharrishmc/dev
Bit manipulation imperas config, fsqrt code changes to match chapter
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2023-11-08 08:27:15 -08:00 |
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David Harris
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b1994f12fa
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Merge pull request #456 from naichewa/main
fifo fixes and edge case testing
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2023-11-08 02:54:06 -08:00 |
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naichewa
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a5837eb62c
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fifo fixes and edge case testing
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2023-11-07 17:59:46 -08:00 |
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David Harris
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637cc3b78a
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Reparitioned sign logic in fdivsqrt to match paper
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2023-11-06 14:11:42 -08:00 |
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David Harris
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2b183020d5
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Fixed bit manpulation on imperas config
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2023-11-06 14:11:01 -08:00 |
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Rose Thompson
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380694293f
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Merge pull request #453 from davidharrishmc/dev
Fixed regression error of watchdog timeout when PCM is optimized out of the IFU
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2023-11-05 15:53:57 -08:00 |
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David Harris
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bddd2d573e
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Shortened path to PCSrcE in logger to avoid problematic hierarchical reference
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2023-11-05 07:06:53 -08:00 |
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David Harris
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9c4a7866b8
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Fixed Svnapot_page_mask for imperas.ic
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2023-11-05 06:51:01 -08:00 |
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David Harris
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b0dbf3a984
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Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue
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2023-11-04 20:36:05 -07:00 |
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David Harris
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568aa3c4a6
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Verilator improvements
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2023-11-04 03:21:07 -07:00 |
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David Harris
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4de21c206f
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-03 16:04:10 -07:00 |
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David Harris
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d067b735e8
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Merge pull request #454 from naichewa/spi
add SPI to cvw/main
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2023-11-03 16:02:57 -07:00 |
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naichewa
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75f1c07022
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merge main, pull /A/ tests
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2023-11-03 13:16:19 -07:00 |
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naichewa
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6cdeb671bb
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Merge branch 'main' into spi
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2023-11-03 13:15:15 -07:00 |
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David Harris
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7a56a66927
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set default USE_SRAM=0 in memories; cleaned up synthesis script grep for cvw_t
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2023-11-03 06:37:05 -07:00 |
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David Harris
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1f2899de14
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Modified rams to take USE_SRAM rather than P to facilitate synthesis
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2023-11-03 05:44:13 -07:00 |
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David Harris
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dd072c80f2
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Updated testbenches to capture InstrM because it may be optimized out of IFU
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2023-11-03 05:24:15 -07:00 |
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David Harris
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402538e13c
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Temporary fix of InstrM to prevent testbench hanging
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2023-11-03 04:59:44 -07:00 |
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David Harris
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09aebbf252
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Fixed regression error of watchdog timeout when PCM is optimized out of the IFU
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2023-11-03 04:38:27 -07:00 |
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naichewa
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4651b807ed
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added test cases
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2023-11-02 15:43:08 -07:00 |
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naichewa
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29e42b21df
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added test cases
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2023-11-02 15:42:28 -07:00 |
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Rose Thompson
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455b78362c
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Merge pull request #449 from davidharrishmc/dev
Synthesis cleanup
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2023-11-02 12:26:55 -05:00 |
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David Harris
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bf65ce0f9f
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Removed .gitattributes
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2023-11-01 17:50:44 -07:00 |
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naichewa
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a08356fdaa
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correct exclusion tags and reset testbench
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2023-11-01 10:34:39 -07:00 |
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naichewa
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e3d8162279
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harris code review 3
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2023-11-01 10:14:15 -07:00 |
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David Harris
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31d9ec08cb
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Improved comments about memory read paths
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2023-11-01 07:00:17 -07:00 |
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naichewa
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9aa8a7af3e
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comments, more test cases
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2023-11-01 01:26:34 -07:00 |
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naichewa
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fefb5adb8f
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code review harris
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2023-10-31 12:27:41 -07:00 |
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David Harris
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dccd7bf5ee
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Fixes to config extraction
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2023-10-31 06:27:55 -07:00 |
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David Harris
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5112bfed19
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130 nm synthesis script improvements
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2023-10-30 20:57:35 -07:00 |
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David Harris
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680fb3f30b
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Conditionally instantiate hardware in ifu
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2023-10-30 20:55:00 -07:00 |
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David Harris
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afabc52b61
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Gated InstrOrigM and PCMReg when not needed
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2023-10-30 20:05:37 -07:00 |
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David Harris
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2d17a991d8
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rom1p1r code cleanup
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2023-10-30 19:47:49 -07:00 |
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David Harris
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3f7c67882f
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rom1p1r code cleanup
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2023-10-30 19:46:38 -07:00 |
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David Harris
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90a178e31e
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Made 2-bit AdrReg conditional on being needed
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2023-10-30 19:13:43 -07:00 |
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naichewa
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7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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naichewa
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2330f4ee63
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hardware interlock
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2023-10-30 17:00:20 -07:00 |
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Rose Thompson
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89de8cd23c
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Merge pull request #445 from davidharrishmc/dev
Fix issue 444; no delegating misaligned instructions if they can't happen
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2023-10-30 12:25:42 -05:00 |
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David Harris
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f6a7f707bd
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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David Harris
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27b8ebb9bd
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Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported.
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2023-10-30 07:06:34 -07:00 |
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Rose Thompson
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50a1d731c0
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Merge pull request #443 from davidharrishmc/dev
Wrapper synthesis fix.
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2023-10-27 09:25:06 -05:00 |
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